Synchronization of two AD9361 devices for DoA Estimation Applications [No MCS] [via XTALN, not RXLO]

Dear all,

I'm trying to achieve inter-board RF-synchronization of two AD9361 devices based on an after-market modification of the SDR system named: Microphase ANTSDR E310-AD9361 [Link for more details: https://www.aliexpress.com/item/1005003181244737.html]. According to the board schematic [https://github.com/MicroPhase/antsdr-fw/blob/master/schematic/ant_e310_Public.pdf], the clock structure feeds both the Xilinx Zynq 7020 AND the AD9361 with a 40 MHz clock signal spitted from a clock-buffer (detailed in sheet 13 of its schematic).

My main goal is to form a 4x4 SDR out of two ANTSDR E310s (2 x AD9361). My procedure is to apply a low noise/jitter clock source [Using the solution "Clock Card 10 based on ESP32" found in: https://coherent-receiver.com/products/rtl-sdr-extension-card/expansion-card ] to replace the two onboard TCXOs.

Pictures to further explain that:

Picture 1: Block Diagram of the clock structure of ANTSDR E310-AD9361 and the suggested HW modification.

Picture 2: HW overview of the system.

Picture 3: ANTSDR-E310 Clock Circuit Diagram.

My target is to use the 4x4 SDR system for Direction Finding Algorithms research. I've looked at the Multi-Chip Sync. (MCS) described at [https://www.youtube.com/watch?v=VFqg6eN2ACE&t=945s] as well as read the procedure in the UG-570 document.

My question is: (more or less) Will this work?

Q1. Regarding the "hidden-from-the-block-diagram" divider in the path of the RXLO clock pin [explained by Dr. Travis Collins in: https://www.youtube.com/watch?v=VFqg6eN2ACE&t=1111s], do I need to perform the 0/180 degrees phase ambiguity correction that results from the random start-up phase of the divider, given that I am feeding the external LO into the XTALN pin?

Picture 4: Dr. Travis Collins Presentation Question: How will the AD9361 perform if we feed the common synchronization clock in the XTALN pin (rather than the RXLO path).

In another words: Regarding the XTALN clock_in path, do I need to worry about any ambiguities?

2. Will feeding a common [low jitter "0.2ppm", 40 MHz, 3Vp-p, through two matched-length IPEX cables] clock signal to two AD9361 devices in the XTALN pin makes it a viable Direction of Arrival Estimation research-ready SDR platform? I understand that time sync via correlation needs to be done for the 2 x 2-RX I-Q streams obtained from two individual boards, but is there anything else I'm missing here?

Best regards,

RedA3