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Phase Difference in AD9361 Multichip Synchronization

Hello,

I understand that RF phase synchronization is not possible across multiple AD9361 chips; however, from reading your materials it sounds like this is mainly due to the div-by-2 array in the RF PLL. This makes it seem like the phase difference in 2 synchronized AD9361 chips would be predictable based on the division ratio. For example, if the RF frequency is set to 3 GHz - 6 GHz, it would be expected that the phase difference would always be either 0 or 180 degrees (assuming both RF paths are equal lengths), or a multiple of 90 deg if set between 1.5 - 3 GHz. Is this a correct assumption? If so, have you collected data showing this kind of phase difference predictability?

  • For the external RF PLL case I think your understanding is correct.

    However let's move this question to the AD9361 design community for further insights.

    -Michael

  • External LO vs Internal LO Generation

    The AD9361 has no mechanism to phase align multiple transceivers together, even when using an external LO. When using the internal LOs multiple transceivers will have a random phase relationship, which will change when LO is changed, sample rate is changed, gain (in some cases) is changed, and even during quadrature tracking. When an external LO is used, like with the ADF5355 on the FMComms5 development system, the transceiver still will have a random phase relation, but it is limited to an 0 or 180 degree offset. This offset is due to the input divider on the external LO input pins and cannot be bypassed. This phase relationship is randomized when the transceivers are power cycled or the power of the external LO is reduced to a certain point. This can happen even with an unmuted ADF5355 during large frequency changes.

    Please refer to the below for the preformance plot on the phase difference.

    https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/phase-sync

    Please refer to the below section from UG-570 document.

  • In this webinar (https://www.analog.com/en/education/education-library/webcasts/developing-multiple-input-multiple-output.html) the reason given for not being able to synchronize RF LO's is because the "Sync pulse does not synchronize the divide by 2 array (pictured below), meaning each division can occur on either the rising or falling edge of the clock. This introduces a phase ambiguity dependent on the division ratio. Divide by 2, can only have a phase ambiguity of 0 or 180, while a 128 division would have a phase ambiguity that can be any multiple of 2.8125-degrees." 

    This statement implies that upon power cycles, if I always set the LO frequency to the same things, lets say 3 GHz for an example, and run synchronization that the differential phase across chips would always be some constant value based on hardware variations + some variable phase difference that is always a multiple of a predictable value, e.g. 360/(n^2) so a multiple of 90 degrees in the 3 GHz example. Is there another reason that the phase variation would be more random than this? e.g. be due to something other than the div-by-2 array which was stated in the above video? I am not asking for phase performance of the FMComms5 specifically, but more generally referenced to two ad9361 transceiver chips that use baseband synchronization but do not use the FMComms5 specific phase sync solution.

     

  • As i mentioned in my previous reply, if you are using external LO then the LO divider value is set to 2 and this can have phase values of 0-180 degrees.

    If you are using using internal LO then accroding to the LO divider value the phase can change,

    Other than this the phase can change at the baseband data interface if you are using more than one AD9361. The over come the phase difference at the data interface MCS feature can be used.

  • My question is regarding using the internal LO and the MCS feature.

    Your response: "If you are using using internal LO then according to the LO divider value the phase can change," and any other phase difference should be resolved by using the MCS feature?

    Again, this implies the differential phase between two AD9361's that have had their baseband PLLs successfully synchronized should have a difference in phase depending on the divider value; therefore, If I am using a frequency of 3 GHz my change in differential phase over power cycles + MCS should always be some multiple of 90 degrees (360/2/2). But we are not seeing that in our set up and I want to understand if we have some other error in our system that makes it behave differently from what should be expected or if we just shouldn't expect to see that because the phase difference is actually caused by something other than the LO divider value as you say.

  • In the case of multiple AD9361 , the VCO phase of each transceiver can be different  (Random) from boot up to Boot up. We do not have RF PLL phase sync feature (Available with ADRV9009 and ADRV9026) in AD9361.

    So from power up to power up you will see difference in phase between transceivers and you need to calibrate at each power up,

  • Hi @vinod @engCK123 I have a similar question.

    I understand the concept that RF PLL phase sync feature is not available in ad9361. 

    I am trying to implement QPSK modulation on ad9361. Now when I try to receive the modulated signal even in loopback there is random phase shift, like sometimes its exactly 180 out of phase or other time its some multiple of 90 degree. Though I am sending my modulated signal in I Q form but with each power up there is different behavior of phase. 

    In UG570 I have read that we have separate PLLs for TX and RX. Is it the reason why I don't get synchronized phase or do I have to do something else?

  • You will see this phase difference of 0 or 180 degree with each power up because of the LO dividers coming up in different phase with every power up.

    In UG570 I have read that we have separate PLLs for TX and RX. Is it the reason why I don't get synchronized phase or do I have to do something else?

    Yes. Even if you use external LO to achieve synchronization between the two RFPLL's, still you will see the 180 degree phase shift with every power up again because of the LO dividers. You need to compensate for the phase shift in baseband.

  • @Sirmoyi  can I achieve phase synchronization using some external hardware for it or I'll have to do compensate it in baseband. 

    Since this phase difference is random so will it be easily compensated in baseband?