My requirement has sampling rates <500KHz, I would like to know the minimum and maximum sampling rate supported by 2T2R AD9361 device ?
I have been told that clock which is given by 9361 is 4 times the datarate and I see in the existing design the single ended version of RX differential clock which is coming to FPGA(kintex_ultrasacle) is used as IQ transmit/receive sample clock.
4 times the rate is it because to support 2T/2R LVDS interface interleaving as according to this diagram?
Does this (samplingrate x 4 = clk) apply for any sampling rate configured ?
Thanks in advance.
[edited by: rakshi at 2:16 PM (GMT -5) on 17 Feb 2021]