Use the second Rx/Tx Channel in AD9361

Hello, I am using a ADRV9361 in my application, basically I wanted to use two channels of AD9361 (both rx and tx). I was working with just one Rx and one Tx at this moment. Now i want to use the second rx and tx available. How can i use it ?  To configurate the first channel i send this command with Putty:


mount /dev/mmcblk0p1 /media/boot

cd /sys/bus/iio/devices/iio\:device0

echo manual > in_voltage0_gain_control_mode

echo 40 > in_voltage0_hardwaregain

echo 0 > out_voltage0_hardwaregain

echo 0 > /sys/bus/iio/devices/iio\:device2/buffer/enable

echo 900000000 > out_altvoltage1_TX_LO_frequency

echo 900000000 > out_altvoltage0_RX_LO_frequency

echo 61440000 > in_voltage_sampling_frequency

echo 61440000 > out_voltage_sampling_frequency

echo 57000000 > in_voltage_rf_bandwidth

echo 57000000 > out_voltage_rf_bandwidth


echo 1 > /sys/bus/iio/devices/iio\:device2/scan_elements/out_voltage0_en

echo 1 > /sys/bus/iio/devices/iio\:device2/scan_elements/out_voltage1_en

echo 1 > /sys/bus/iio/devices/iio\:device2/buffer/enable

In my FPGA design i do the Loopback internally. To simplify the post ADC and DAC of each channel are connected:

 Now, Whats the next step to use the second rx/tx ?



ed
[edited by: FCAG_123 at 1:18 PM (GMT -5) on 1 Feb 2021]
  • 0
    •  Analog Employees 
    on Feb 2, 2021 5:06 AM 2 months ago

    You have to enable the 2T2R mode in the init structure before initializing the chip using adi,2rx-2tx-mode-enable.

    Refer below link:

    https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9361-customization 

    https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9361 

  • Hi, thank you for answer me.
    I saw in the dtb  that i have enable the 2T2R by default, i never touch the dtb at the moment:


    I tryied to enable the other 2 (out_voltage2_en  and out_voltage3_en)

    Its says is busy, i dont know if im doing something wrong.

    I can activate out_voltage0_en and out_voltage1_en to use the first channel.

    Best,
    FC

  • 0
    •  Analog Employees 
    on Feb 2, 2021 12:43 PM 2 months ago in reply to FCAG_123

    You have to set that parameter(adi,2rx-2tx-mode-enable) to 1 in the device tree. By default, 1T1R mode is enabled and hence you are facing this issue.

  • How can i set to 1 in the devicetree ? i thought that is not commented ( using "//") so it's enabled,i dont find any sentence that say  " 1T1R ", I will add the dts file as txt.
    I dont have experience modifying dtb

     

    devicetree.txt
    /dts-v1/;
    
    / {
    	#address-cells = <0x1>;
    	#size-cells = <0x1>;
    	compatible = "xlnx,zynq-7000";
    	interrupt-parent = <0x1>;
    	model = "Analog Devices ADRV9361-Z7035 (Z7035/AD9361)";
    
    	cpus {
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    
    		cpu@0 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <0x0>;
    			clocks = <0x2 0x3>;
    			clock-latency = <0x3e8>;
    			cpu0-supply = <0x3>;
    			operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
    		};
    
    		cpu@1 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <0x1>;
    			clocks = <0x2 0x3>;
    		};
    	};
    
    	fpga-full {
    		compatible = "fpga-region";
    		fpga-mgr = <0x4>;
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges;
    	};
    
    	pmu@f8891000 {
    		compatible = "arm,cortex-a9-pmu";
    		interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
    		interrupt-parent = <0x1>;
    		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
    	};
    
    	fixedregulator {
    		compatible = "regulator-fixed";
    		regulator-name = "VCCPINT";
    		regulator-min-microvolt = <0xf4240>;
    		regulator-max-microvolt = <0xf4240>;
    		regulator-boot-on;
    		regulator-always-on;
    		linux,phandle = <0x3>;
    		phandle = <0x3>;
    	};
    
    	amba {
    		u-boot,dm-pre-reloc;
    		compatible = "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		interrupt-parent = <0x1>;
    		ranges;
    
    		adc@f8007100 {
    			compatible = "xlnx,zynq-xadc-1.00.a";
    			reg = <0xf8007100 0x20>;
    			interrupts = <0x0 0x7 0x4>;
    			interrupt-parent = <0x1>;
    			clocks = <0x2 0xc>;
    		};
    
    		can@e0008000 {
    			compatible = "xlnx,zynq-can-1.0";
    			status = "disabled";
    			clocks = <0x2 0x13 0x2 0x24>;
    			clock-names = "can_clk", "pclk";
    			reg = <0xe0008000 0x1000>;
    			interrupts = <0x0 0x1c 0x4>;
    			interrupt-parent = <0x1>;
    			tx-fifo-depth = <0x40>;
    			rx-fifo-depth = <0x40>;
    		};
    
    		can@e0009000 {
    			compatible = "xlnx,zynq-can-1.0";
    			status = "disabled";
    			clocks = <0x2 0x14 0x2 0x25>;
    			clock-names = "can_clk", "pclk";
    			reg = <0xe0009000 0x1000>;
    			interrupts = <0x0 0x33 0x4>;
    			interrupt-parent = <0x1>;
    			tx-fifo-depth = <0x40>;
    			rx-fifo-depth = <0x40>;
    		};
    
    		gpio@e000a000 {
    			compatible = "xlnx,zynq-gpio-1.0";
    			#gpio-cells = <0x2>;
    			clocks = <0x2 0x2a>;
    			gpio-controller;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x14 0x4>;
    			reg = <0xe000a000 0x1000>;
    			linux,phandle = <0x6>;
    			phandle = <0x6>;
    		};
    
    		i2c@e0004000 {
    			compatible = "cdns,i2c-r1p10";
    			status = "disabled";
    			clocks = <0x2 0x26>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x19 0x4>;
    			reg = <0xe0004000 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		i2c@e0005000 {
    			compatible = "cdns,i2c-r1p10";
    			status = "disabled";
    			clocks = <0x2 0x27>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x30 0x4>;
    			reg = <0xe0005000 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		interrupt-controller@f8f01000 {
    			compatible = "arm,cortex-a9-gic";
    			#interrupt-cells = <0x3>;
    			interrupt-controller;
    			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
    			linux,phandle = <0x1>;
    			phandle = <0x1>;
    		};
    
    		cache-controller@f8f02000 {
    			compatible = "arm,pl310-cache";
    			reg = <0xf8f02000 0x1000>;
    			interrupts = <0x0 0x2 0x4>;
    			arm,data-latency = <0x3 0x2 0x2>;
    			arm,tag-latency = <0x2 0x2 0x2>;
    			cache-unified;
    			cache-level = <0x2>;
    		};
    
    		memory-controller@f8006000 {
    			compatible = "xlnx,zynq-ddrc-a05";
    			reg = <0xf8006000 0x1000>;
    		};
    
    		ocmc@f800c000 {
    			compatible = "xlnx,zynq-ocmc-1.0";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x3 0x4>;
    			reg = <0xf800c000 0x1000>;
    		};
    
    		serial@e0000000 {
    			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
    			status = "disabled";
    			clocks = <0x2 0x17 0x2 0x28>;
    			clock-names = "uart_clk", "pclk";
    			reg = <0xe0000000 0x1000>;
    			interrupts = <0x0 0x1b 0x4>;
    		};
    
    		serial@e0001000 {
    			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
    			status = "okay";
    			clocks = <0x2 0x18 0x2 0x29>;
    			clock-names = "uart_clk", "pclk";
    			reg = <0xe0001000 0x1000>;
    			interrupts = <0x0 0x32 0x4>;
    		};
    
    		spi@e0006000 {
    			compatible = "xlnx,zynq-spi-r1p6";
    			reg = <0xe0006000 0x1000>;
    			status = "okay";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x1a 0x4>;
    			clocks = <0x2 0x19 0x2 0x22>;
    			clock-names = "ref_clk", "pclk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    
    			ad9361-phy@0 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				#clock-cells = <0x1>;
    				compatible = "adi,ad9361";
    				reg = <0x0>;
    				spi-cpha;
    				spi-max-frequency = <0x989680>;
    				clocks = <0x5 0x0>;
    				clock-names = "ad9361_ext_refclk";
    				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
    				adi,digital-interface-tune-skip-mode = <0x0>;
    				adi,pp-tx-swap-enable;
    				adi,pp-rx-swap-enable;
    				adi,rx-frame-pulse-mode-enable;
    				adi,lvds-mode-enable;
    				adi,lvds-bias-mV = <0x96>;
    				adi,lvds-rx-onchip-termination-enable;
    				adi,rx-data-delay = <0x4>;
    				adi,tx-fb-clock-delay = <0x7>;
    				adi,xo-disable-use-ext-refclk-enable;
    				adi,2rx-2tx-mode-enable;
    				adi,frequency-division-duplex-mode-enable;
    				adi,rx-rf-port-input-select = <0x0>;
    				adi,tx-rf-port-input-select = <0x0>;
    				adi,tx-attenuation-mdB = <0x2710>;
    				adi,tx-lo-powerdown-managed-enable;
    				adi,rf-rx-bandwidth-hz = <0x112a880>;
    				adi,rf-tx-bandwidth-hz = <0x112a880>;
    				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
    				adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
    				adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
    				adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
    				adi,gc-rx1-mode = <0x2>;
    				adi,gc-rx2-mode = <0x2>;
    				adi,gc-adc-ovr-sample-size = <0x4>;
    				adi,gc-adc-small-overload-thresh = <0x2f>;
    				adi,gc-adc-large-overload-thresh = <0x3a>;
    				adi,gc-lmt-overload-high-thresh = <0x320>;
    				adi,gc-lmt-overload-low-thresh = <0x2c0>;
    				adi,gc-dec-pow-measurement-duration = <0x2000>;
    				adi,gc-low-power-thresh = <0x18>;
    				adi,mgc-inc-gain-step = <0x2>;
    				adi,mgc-dec-gain-step = <0x2>;
    				adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
    				adi,agc-attack-delay-extra-margin-us = <0x1>;
    				adi,agc-outer-thresh-high = <0x5>;
    				adi,agc-outer-thresh-high-dec-steps = <0x2>;
    				adi,agc-inner-thresh-high = <0xa>;
    				adi,agc-inner-thresh-high-dec-steps = <0x1>;
    				adi,agc-inner-thresh-low = <0xc>;
    				adi,agc-inner-thresh-low-inc-steps = <0x1>;
    				adi,agc-outer-thresh-low = <0x12>;
    				adi,agc-outer-thresh-low-inc-steps = <0x2>;
    				adi,agc-adc-small-overload-exceed-counter = <0xa>;
    				adi,agc-adc-large-overload-exceed-counter = <0xa>;
    				adi,agc-adc-large-overload-inc-steps = <0x2>;
    				adi,agc-lmt-overload-large-exceed-counter = <0xa>;
    				adi,agc-lmt-overload-small-exceed-counter = <0xa>;
    				adi,agc-lmt-overload-large-inc-steps = <0x2>;
    				adi,agc-gain-update-interval-us = <0x3e8>;
    				adi,fagc-dec-pow-measurement-duration = <0x40>;
    				adi,fagc-lp-thresh-increment-steps = <0x1>;
    				adi,fagc-lp-thresh-increment-time = <0x5>;
    				adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
    				adi,fagc-final-overrange-count = <0x3>;
    				adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
    				adi,fagc-lmt-final-settling-steps = <0x1>;
    				adi,fagc-lock-level = <0xa>;
    				adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
    				adi,fagc-lock-level-lmt-gain-increase-enable;
    				adi,fagc-lpf-final-settling-steps = <0x1>;
    				adi,fagc-optimized-gain-offset = <0x5>;
    				adi,fagc-power-measurement-duration-in-state5 = <0x40>;
    				adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
    				adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
    				adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
    				adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
    				adi,fagc-rst-gla-large-adc-overload-enable;
    				adi,fagc-rst-gla-large-lmt-overload-enable;
    				adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
    				adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
    				adi,fagc-state-wait-time-ns = <0x104>;
    				adi,fagc-use-last-lock-level-for-set-gain-enable;
    				adi,rssi-restart-mode = <0x3>;
    				adi,rssi-delay = <0x1>;
    				adi,rssi-wait = <0x1>;
    				adi,rssi-duration = <0x3e8>;
    				adi,ctrl-outs-index = <0x0>;
    				adi,ctrl-outs-enable-mask = <0xff>;
    				adi,temp-sense-measurement-interval-ms = <0x3e8>;
    				adi,temp-sense-offset-signed = <0xce>;
    				adi,temp-sense-periodic-measurement-enable;
    				adi,aux-dac-manual-mode-enable;
    				adi,aux-dac1-default-value-mV = <0x0>;
    				adi,aux-dac1-rx-delay-us = <0x0>;
    				adi,aux-dac1-tx-delay-us = <0x0>;
    				adi,aux-dac2-default-value-mV = <0x0>;
    				adi,aux-dac2-rx-delay-us = <0x0>;
    				adi,aux-dac2-tx-delay-us = <0x0>;
    				en_agc-gpios = <0x6 0x62 0x0>;
    				sync-gpios = <0x6 0x63 0x0>;
    				reset-gpios = <0x6 0x64 0x0>;
    				enable-gpios = <0x6 0x65 0x0>;
    				txnrx-gpios = <0x6 0x66 0x0>;
    				linux,phandle = <0xc>;
    				phandle = <0xc>;
    			};
    		};
    
    		spi@e0007000 {
    			compatible = "xlnx,zynq-spi-r1p6";
    			reg = <0xe0007000 0x1000>;
    			status = "disabled";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x31 0x4>;
    			clocks = <0x2 0x1a 0x2 0x23>;
    			clock-names = "ref_clk", "pclk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		spi@e000d000 {
    			clock-names = "ref_clk", "pclk";
    			clocks = <0x2 0xa 0x2 0x2b>;
    			compatible = "xlnx,zynq-qspi-1.0";
    			status = "okay";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x13 0x4>;
    			reg = <0xe000d000 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			is-dual = <0x0>;
    			num-cs = <0x1>;
    
    			ps7-qspi@0 {
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				spi-tx-bus-width = <0x1>;
    				spi-rx-bus-width = <0x4>;
    				compatible = "n25q256a", "jedec,spi-nor";
    				reg = <0x0>;
    				spi-max-frequency = <0x2faf080>;
    
    				partition@qspi-fsbl-uboot {
    					label = "qspi-fsbl-uboot";
    					reg = <0x0 0xe0000>;
    				};
    
    				partition@qspi-uboot-env {
    					label = "qspi-uboot-env";
    					reg = <0xe0000 0x20000>;
    				};
    
    				partition@qspi-linux {
    					label = "qspi-linux";
    					reg = <0x100000 0x500000>;
    				};
    
    				partition@qspi-device-tree {
    					label = "qspi-device-tree";
    					reg = <0x600000 0x20000>;
    				};
    
    				partition@qspi-rootfs {
    					label = "qspi-rootfs";
    					reg = <0x620000 0xce0000>;
    				};
    
    				partition@qspi-bitstream {
    					label = "qspi-bitstream";
    					reg = <0x1300000 0xd00000>;
    				};
    			};
    		};
    
    		memory-controller@e000e000 {
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			clock-names = "memclk", "aclk";
    			clocks = <0x2 0xb 0x2 0x2c>;
    			compatible = "arm,pl353-smc-r2p1";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x12 0x4>;
    			ranges;
    			reg = <0xe000e000 0x1000>;
    
    			flash@e1000000 {
    				status = "disabled";
    				compatible = "arm,pl353-nand-r2p1";
    				reg = <0xe1000000 0x1000000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    			};
    
    			flash@e2000000 {
    				status = "disabled";
    				compatible = "cfi-flash";
    				reg = <0xe2000000 0x2000000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    			};
    		};
    
    		ethernet@e000b000 {
    			compatible = "cdns,zynq-gem", "cdns,gem";
    			reg = <0xe000b000 0x1000>;
    			status = "okay";
    			interrupts = <0x0 0x16 0x4>;
    			clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
    			clock-names = "pclk", "hclk", "tx_clk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			phy-handle = <0x7>;
    			phy-mode = "rgmii-id";
    
    			phy@0 {
    				device_type = "ethernet-phy";
    				reg = <0x0>;
    				marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;
    				linux,phandle = <0x7>;
    				phandle = <0x7>;
    			};
    		};
    
    		ethernet@e000c000 {
    			compatible = "cdns,zynq-gem", "cdns,gem";
    			reg = <0xe000c000 0x1000>;
    			status = "disabled";
    			interrupts = <0x0 0x2d 0x4>;
    			clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
    			clock-names = "pclk", "hclk", "tx_clk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		mmc@e0100000 {
    			compatible = "arasan,sdhci-8.9a";
    			status = "okay";
    			clock-names = "clk_xin", "clk_ahb";
    			clocks = <0x2 0x15 0x2 0x20>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x18 0x4>;
    			reg = <0xe0100000 0x1000>;
    			disable-wp;
    		};
    
    		mmc@e0101000 {
    			compatible = "arasan,sdhci-8.9a";
    			status = "disabled";
    			clock-names = "clk_xin", "clk_ahb";
    			clocks = <0x2 0x16 0x2 0x21>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x2f 0x4>;
    			reg = <0xe0101000 0x1000>;
    		};
    
    		slcr@f8000000 {
    			u-boot,dm-pre-reloc;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
    			reg = <0xf8000000 0x1000>;
    			ranges;
    			linux,phandle = <0x8>;
    			phandle = <0x8>;
    
    			clkc@100 {
    				u-boot,dm-pre-reloc;
    				#clock-cells = <0x1>;
    				compatible = "xlnx,ps7-clkc";
    				fclk-enable = <0xf>;
    				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
    				reg = <0x100 0x100>;
    				ps-clk-frequency = <0x1fca055>;
    				linux,phandle = <0x2>;
    				phandle = <0x2>;
    			};
    
    			rstc@200 {
    				compatible = "xlnx,zynq-reset";
    				reg = <0x200 0x48>;
    				#reset-cells = <0x1>;
    				syscon = <0x8>;
    			};
    
    			pinctrl@700 {
    				compatible = "xlnx,pinctrl-zynq";
    				reg = <0x700 0x200>;
    				syscon = <0x8>;
    			};
    		};
    
    		dmac@f8003000 {
    			compatible = "arm,pl330", "arm,primecell";
    			reg = <0xf8003000 0x1000>;
    			interrupt-parent = <0x1>;
    			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
    			interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
    			#dma-cells = <0x1>;
    			#dma-channels = <0x8>;
    			#dma-requests = <0x4>;
    			clocks = <0x2 0x1b>;
    			clock-names = "apb_pclk";
    		};
    
    		devcfg@f8007000 {
    			compatible = "xlnx,zynq-devcfg-1.0";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x8 0x4>;
    			reg = <0xf8007000 0x100>;
    			clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
    			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
    			syscon = <0x8>;
    			linux,phandle = <0x4>;
    			phandle = <0x4>;
    		};
    
    		efuse@f800d000 {
    			compatible = "xlnx,zynq-efuse";
    			reg = <0xf800d000 0x20>;
    		};
    
    		timer@f8f00200 {
    			compatible = "arm,cortex-a9-global-timer";
    			reg = <0xf8f00200 0x20>;
    			interrupts = <0x1 0xb 0x301>;
    			interrupt-parent = <0x1>;
    			clocks = <0x2 0x4>;
    		};
    
    		timer@f8001000 {
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
    			compatible = "cdns,ttc";
    			clocks = <0x2 0x6>;
    			reg = <0xf8001000 0x1000>;
    		};
    
    		timer@f8002000 {
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
    			compatible = "cdns,ttc";
    			clocks = <0x2 0x6>;
    			reg = <0xf8002000 0x1000>;
    		};
    
    		timer@f8f00600 {
    			interrupt-parent = <0x1>;
    			interrupts = <0x1 0xd 0x301>;
    			compatible = "arm,cortex-a9-twd-timer";
    			reg = <0xf8f00600 0x20>;
    			clocks = <0x2 0x4>;
    		};
    
    		usb@e0002000 {
    			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
    			status = "okay";
    			clocks = <0x2 0x1c>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x15 0x4>;
    			reg = <0xe0002000 0x1000>;
    			phy_type = "ulpi";
    			dr_mode = "host";
    			xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
    		};
    
    		usb@e0003000 {
    			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
    			status = "disabled";
    			clocks = <0x2 0x1d>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x2c 0x4>;
    			reg = <0xe0003000 0x1000>;
    			phy_type = "ulpi";
    		};
    
    		watchdog@f8005000 {
    			clocks = <0x2 0x2d>;
    			compatible = "cdns,wdt-r1p2";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x9 0x1>;
    			reg = <0xf8005000 0x1000>;
    			timeout-sec = <0xa>;
    		};
    	};
    
    	aliases {
    		ethernet0 = "/amba/ethernet@e000b000";
    		serial0 = "/amba/serial@e0001000";
    	};
    
    	memory {
    		device_type = "memory";
    		reg = <0x0 0x40000000>;
    	};
    
    	chosen {
    		linux,stdout-path = "/amba@0/uart@E0001000";
    	};
    
    	clocks {
    
    		clock@0 {
    			#clock-cells = <0x0>;
    			compatible = "adjustable-clock";
    			clock-frequency = <0x2625a00>;
    			clock-accuracy = <0x30d40>;
    			clock-output-names = "XO_40MHz";
    			linux,phandle = <0x9>;
    			phandle = <0x9>;
    		};
    
    		clock@2 {
    			#clock-cells = <0x0>;
    			compatible = "fixed-clock";
    			clock-frequency = <0x16e3600>;
    			clock-output-names = "24MHz";
    			linux,phandle = <0xa>;
    			phandle = <0xa>;
    		};
    	};
    
    	ad9361-refclk-gpio-gate@0 {
    		#clock-cells = <0x0>;
    		compatible = "gpio-gate-clock";
    		clocks = <0x9>;
    		enable-gpios = <0x6 0x69 0x0>;
    		clk-set-rate-parent-enable;
    		clock-output-names = "ad9361_ext_refclk";
    		linux,phandle = <0x5>;
    		phandle = <0x5>;
    	};
    
    	usb-ulpe-gpio-gate@0 {
    		#clock-cells = <0x0>;
    		compatible = "gpio-gate-clock";
    		clocks = <0xa>;
    		enable-gpios = <0x6 0x9 0x1>;
    	};
    
    	fpga-axi@0 {
    		compatible = "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges;
    
    		i2c@41600000 {
    			compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
    			reg = <0x41600000 0x10000>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x3a 0x4>;
    			clocks = <0x2 0xf>;
    			clock-names = "pclk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    
    			adm1166@68 {
    				compatible = "adi,adm1166";
    				reg = <0x68>;
    			};
    
    			ad7291-bob@2f {
    				compatible = "adi,ad7291";
    				reg = <0x2f>;
    			};
    
    			eeprom@50 {
    				compatible = "at24,24c32";
    				reg = <0x50>;
    			};
    		};
    
    		dma@7c400000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x7c400000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x39 0x0>;
    			clocks = <0x2 0x10>;
    			linux,phandle = <0xb>;
    			phandle = <0xb>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x2>;
    					adi,destination-bus-width = <0x40>;
    					adi,destination-bus-type = <0x0>;
    				};
    			};
    		};
    
    		dma@7c420000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x7c420000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x38 0x0>;
    			clocks = <0x2 0x10>;
    			linux,phandle = <0xd>;
    			phandle = <0xd>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x0>;
    					adi,destination-bus-width = <0x40>;
    					adi,destination-bus-type = <0x2>;
    				};
    			};
    		};
    
    		cf-ad9361-lpc@79020000 {
    			compatible = "adi,axi-ad9361-6.00.a";
    			reg = <0x79020000 0x6000>;
    			dmas = <0xb 0x0>;
    			dma-names = "rx";
    			spibus-connected = <0xc>;
    		};
    
    		cf-ad9361-dds-core-lpc@79024000 {
    			compatible = "adi,axi-ad9361-dds-6.00.a";
    			reg = <0x79024000 0x1000>;
    			clocks = <0xc 0xd>;
    			clock-names = "sampl_clk";
    			dmas = <0xd 0x0>;
    			dma-names = "tx";
    		};
    
    		mwipcore@43c00000 {
    			compatible = "mathworks,mwipcore-axi4lite-v1.00";
    			reg = <0x43c00000 0xffff>;
    		};
    
    		axi-sysid-0@45000000 {
    			compatible = "adi,axi-sysid-1.00.a";
    			reg = <0x45000000 0x10000>;
    		};
    	};
    
    	leds {
    		compatible = "gpio-leds";
    
    		led0 {
    			label = "led0:green";
    			gpios = <0x6 0x3a 0x0>;
    		};
    
    		led1 {
    			label = "led1:green";
    			gpios = <0x6 0x3b 0x0>;
    		};
    
    		led2 {
    			label = "led2:green";
    			gpios = <0x6 0x3c 0x0>;
    		};
    
    		led3 {
    			label = "led3:green";
    			gpios = <0x6 0x3d 0x0>;
    		};
    	};
    
    	gpio_keys {
    		compatible = "gpio-keys";
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    		autorepeat;
    
    		pb0 {
    			label = "Left";
    			linux,code = <0x69>;
    			gpios = <0x6 0x36 0x0>;
    		};
    
    		pb1 {
    			label = "Right";
    			linux,code = <0x6a>;
    			gpios = <0x6 0x37 0x0>;
    		};
    
    		pb2 {
    			label = "Up";
    			linux,code = <0x67>;
    			gpios = <0x6 0x38 0x0>;
    		};
    
    		pb3 {
    			label = "Down";
    			linux,code = <0x6c>;
    			gpios = <0x6 0x39 0x0>;
    		};
    
    		sw0 {
    			label = "SW0";
    			linux,input-type = <0x5>;
    			linux,code = <0x0>;
    			gpios = <0x6 0x3e 0x0>;
    		};
    
    		sw1 {
    			label = "SW1";
    			linux,input-type = <0x5>;
    			linux,code = <0x1>;
    			gpios = <0x6 0x3f 0x0>;
    		};
    
    		sw2 {
    			label = "SW2";
    			linux,input-type = <0x5>;
    			linux,code = <0x2>;
    			gpios = <0x6 0x40 0x0>;
    		};
    
    		sw3 {
    			label = "SW3";
    			linux,input-type = <0x5>;
    			linux,code = <0x3>;
    			gpios = <0x6 0x41 0x0>;
    		};
    	};
    };
    

    Code:


    adi,2rx-2tx-mode-enable= <1>; 

    Its correct ?

    Best,
    FC

  • 0
    •  Analog Employees 
    on Feb 3, 2021 9:39 AM 2 months ago in reply to FCAG_123

    Yes, set that to 1 and  add that in the dts file and then initialize with the changed device tree and check.

    You have change the .dtb to .dts, change the parameter inside that and then again convert it to .dtb in Linux. Refer the below link for the steps:

    https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynq_tips_tricks?s[]=devictree