AD9364 reference clock voltage dividing

Hi,

I am thinking  using this oscilator(https://abracon.com/Oscillators/AST3TQ-28.pdf ) in AD9364. But voltage level of my oscilator is VOH : 2.4V and VOL = 0.4V. namely Vpp is 2V. I need a capacitive voltage dividing. In this case I am in little confusing.  I read about some post regarding this problem ( https://ez.analog.com/wide-band-rf-transceivers/design-support/f/q-a/80684/ad9361-ref_clk-level/55967#55967). But I am not clear given answers in this post about voltage dividing. Which capacitor value  should ı use for my oscillator for my voltage dividing?

1-) for example, in AD-COMMS5-EBZ,  Vpp is 1.8V and  capacitive divider consists of (39pF and 10pf(internal capacitance))  1.8V *(39pf/(10pf+39pf))= 1.43Vpp(is must be between 0.8v and 1.3v). What is wrong my calculation? it is not in input level obligation

2-) Another question, is it necessarry  for XTALN being VOL =-0.65 and VOH= +0.65V  for VPP =1.3V. Is it possible  VOL : 0.7V and VOH= 2V  for VPP =1.3V?

Thank you



adding
[edited by: gcetinkaya at 9:02 PM (GMT -5) on 27 Jan 2021]