We are planning to operate AD9361 with external 10MHz Sinewave OCXO clock using single ended XTALN (Pin M12) and XTALP (Pin M11) is not connected (leave floating).
In the datasheet it was mentioned the input clock Signal Level 1.3 Vp-p (AC-coupled external oscillator) which in 50Ohms load +6.3dBm.
But in the datasheet there is no minimum and maximum and absolute maximum rating levels for this clock source pin. Please provide the values for the same.
The amplitude of the ref_clk should not exceed 1.3V core supply voltage. On the lower side it should not go lower than 800mVpk-pk.
But in the datasheet Typical clock Signal Level is mentioned as 1.3Vp-p but you have mentioned should not exceed 1.3V core supply voltage.
If we give 1.3Vp-p Sinewave clock in XTALN pin (single ended) than what is the maximum voltage at XTALN pin. That mean what is the internal DC offset biased at XTALN pin?
In our application we need to feed external 10MHz signal 0dBm +/- 3dB directly to AD9361 with some amplifier and attenuator after that, So if 50Ohm shunt termination is planned in XTALN pin then 800mVp-p to 1.3Vp-p corresponds to +2dBm to +6.3dBm alone.
Is it is the operating range of AD9361 external clock?
Yes. 1.3V p-p is the maximum voltage as above that performance degradation will be seen.