In reference manual's 14th page OF AD9364 mentions that " For optimum phase noise it is recommended to operate the scaled clock as close to 80 MHz as possible".
But As can be seen below photos, The lowest phase noise is in 30.72 MHZ. But in 40 mhz, phase noise are worse than in 30.72mhz. This is opposite data according to above statement.. Could you clarify this? Thank you
gcetinkaya said:n this statement 80 mhz, is 80 Mhz scaled clock
Yes, it is scaled clock.
The ref_clk after scaling should be close to 80MHz for best phase noise performance.
The actual clock to the chip is scaled to 61.44MHz(since it is internally doubled) and hence the plot for that ref_clk is better.
THank you for your answer. is this valid in internal clock? For example,AD-FMCOMMS4 has 40mhz crystal. if this crystal's frequency become 80 MHz, would phase noise improve?
Yes. Phase noise will be better for 40MHz .
Namely using 80mhz crystal (which will double 160mhz as internal) are better in terms of phase noise ? Am I right? If so, why dont you use 80MHZ crystal in AD-FMCOMMS4? Using 80mhz crystal has any disadvantages?
Maximum is 80MHz