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AD9361 RF DC Cal Fail

Dear Sir, I have setup the ad_fmcomms3 evb and attached it on FPGA board via FMC connector to build up my wireless application system now. According to the filter design and my system  requirement, I have applied the configuration below:

1、FDD、1T1R、CMOS mode、DDR。

2、DATA_CLK and ADC should be 48MHz for I/Q。

3、Set all decimation factor be 1 to HB3, HB2, HB1, and RFIR to let the ADC_CLK=DATA_CLK=48MHz。Therefore the RX sampling rate is 48 MSPS

4、Select to bypass RFIR and TFIR。

And then AD9361 RF DC CALIBRATION is always failed, it means SPIRead(0x016) [1] is always 0x1. This bit won't be clear to  reach "Cal DONE".

But if I change the filter setting to set decimation factor of HB1 be 2, means to let ADC_CLK=96MHz (DATA_CLK is still 48MHz), the RF DC CALIBRATION will success and done. But this case is not what I want. I need to keep ADC_CLK=DATA_CLK=48MHz。 May sir help to fixed this RF DC CALIBRATION FAIL issue to fullfill my need? Thank you!

Ryan

  • More information is that I have set 0x35 to read control output GPIO to get the status, and found:

    1. ENSM is ALERT(0x5) state before doing the RF DC Cal, and be 0x3 after setting 0x016[1]=0x1

    2. Cal Seq state is 0x3 after setting 0x016[1]=0x1

    3. RF DC Cal state is keeping 0x0 after setting 0x016[1]=0x1

    I think there is something wrong to make the RF DC Cal state in the IDLE state always but I don't know why?

  • Are you using the filter wizard tool to generate profiles?

    Can you share with us the profile with which you are seeing the issue?

  • Hi Sir,

    The configuration script is shown below:

      //reset AD9361
      WRITE(ADSPICTRLADDR, 0x00010000);
      WRITE(ADSPICTRLADDR, 0x00000000);
      WRITE(ADSPICTRLADDR, 0x00010000);
    	
      ryan_printf("\n\r --- AD9361 RFE testing : SPI command register --- \n\r");	
      //************************************************************
      // AD9361 Initialization
      //************************************************************
      //REFCLK_IN: 40.000 MHz
      
      adspi_wr(0x3DF,0x01);	// Required for proper operation
      //ReadPartNumber
      getid();
    		
      adspi_wr(0x2A6,0x0E);	// Enable Master Bias
      adspi_wr(0x2A8,0x0E);	// Set Bandgap Trim
      
      adspi_wr(0x292,0x08);	// Set DCXO Coarse Tune[5:0].  Coarse and Fine nominal values used with eval system.  Other nominal values may be needed in a customer system
      adspi_wr(0x293,0x80);	// Set DCXO Fine Tune [12:5]
      adspi_wr(0x294,0x00);	// Set DCXO Fine Tune [4:0]
      adspi_wr(0x2AB,0x07);	// Set RF PLL reflclk scale to REFCLK * 2
      adspi_wr(0x2AC,0xFF);	// Set RF PLL reflclk scale to REFCLK * 2
      adspi_wr(0x009,0x07);	// Enable Clocks
      //waits 20 ms
      ryan_printf("\n\r --- AD9361 Setting wait 20ms --- \n\r");
      
      // Set BBPLL Frequency: 768.000000
      adspi_wr(0x045,0x00);	// Set BBPLL reflclk scale to REFCLK /1
      adspi_wr(0x046,0x02);	// Set BBPLL Loop Filter Charge Pump current
      adspi_wr(0x048,0xE8);	// Set BBPLL Loop Filter C1, R1
      adspi_wr(0x049,0x5B);	// Set BBPLL Loop Filter R2, C2, C1
      adspi_wr(0x04A,0x35);	// Set BBPLL Loop Filter C3,R2
      adspi_wr(0x04B,0xE0);	// Allow calibration to occur and set cal count to 1024 for max accuracy
      adspi_wr(0x04E,0x10);	// Set calibration clock to REFCLK/4 for more accuracy
      adspi_wr(0x043,0x00);	// BBPLL Freq Word (Fractional[7:0])
      adspi_wr(0x042,0x60);	// BBPLL Freq Word (Fractional[15:8])
      adspi_wr(0x041,0x06);	// BBPLL Freq Word (Fractional[23:16])
      adspi_wr(0x044,0x13);	// BBPLL Freq Word (Integer[7:0])
      adspi_wr(0x03F,0x05);	// Start BBPLL Calibration
      adspi_wr(0x03F,0x01);	// Clear BBPLL start calibration bit
      adspi_wr(0x04C,0x86);	// Increase BBPLL KV and phase margin
      adspi_wr(0x04D,0x01);	// Increase BBPLL KV and phase margin
      adspi_wr(0x04D,0x05);	// Increase BBPLL KV and phase margin
      
      do {
          adspi_rd(0x05E, &rd_data);
          rd_data = (rd_data >> 7) & 0x1;
      }while(rd_data==0x0);			// Check BBPLL locked status  (0x05E[7]==1 is locked)
      
      
      adspi_wr(0x002,0x40);	// Setup Tx Digital Filters/ Channels
      adspi_wr(0x003,0x40);	// ADC=48MHz , Setup Rx Digital Filters/ Channels
      adspi_wr(0x004,0x03);	// Select Rx input pin(A,B,C)/ Tx out pin (A,B)
      adspi_wr(0x00A,0x14);	// ADC=48MHz , Set BBPLL post divide rate
    
      // Setup the Parallel Port (Digital Data Interface)
      adspi_wr(0x010,0xC8);	// I/O Config.  Tx Swap IQ<7>; Rx Swap IQ<6>; Tx CH Swap<5>, Rx CH Swap<4>; Rx Frame Mode<3>; 2R2T bit<2>; Invert data bus<1>; Invert DATA_CLK<0>
      adspi_wr(0x011,0x04);	// I/O Config.  Alt Word Order<7>; -Rx1<6>; -Rx2<5>; -Tx1<4>; -Tx2<3>; Invert Rx Frame<2>; Delay Rx Data<1:0>
      adspi_wr(0x012,0x42);	// I/O Config.  Rx=2*Tx<7>; Swap Ports<6>; SDR<5>; LVDS<4>; Half Duplex<3>; Single Port<2>; Full Port<1>; Swap Bits<0>
      adspi_wr(0x006,0xF0);	// PPORT Rx Delay (adjusts Tco Dataclk->Data). Dataclk Prop Delay<7:4>; Rx Data/Rx Frame Prop Delay<3:0>
      adspi_wr(0x007,0x00);	// PPORT TX Delay (adjusts setup/hold FBCLK->Data)
    
      // Setup AuxDAC
      adspi_wr(0x018,0x00);	// AuxDAC1 Word[9:2]
      adspi_wr(0x019,0x00);	// AuxDAC2 Word[9:2]
      adspi_wr(0x01A,0x00);	// AuxDAC1 Config and Word[1:0]
      adspi_wr(0x01B,0x00);	// AuxDAC2 Config and Word[1:0]
      adspi_wr(0x023,0xFF);	// AuxDAC Manaul/Auto Control
      adspi_wr(0x026,0x00);	// AuxDAC Manual Select Bit/GPO Manual Select
      adspi_wr(0x030,0x00);	// AuxDAC1 Rx Delay
      adspi_wr(0x031,0x00);	// AuxDAC1 Tx Delay
      adspi_wr(0x032,0x00);	// AuxDAC2 Rx Delay
      adspi_wr(0x033,0x00);	// AuxDAC2 Tx Delay
      
      // Setup AuxADC
      adspi_wr(0x00B,0x00);	// Temp Sensor Setup (Offset)
      adspi_wr(0x00C,0x00);	// Temp Sensor Setup (Temp Window)
      adspi_wr(0x00D,0x03);	// Temp Sensor Setup (Periodic Measure)
      adspi_wr(0x00F,0x04);	// Temp Sensor Setup (Decimation)
      adspi_wr(0x01C,0x10);	// AuxADC Setup (Clock Div)
      adspi_wr(0x01D,0x01);	// AuxADC Setup (Decimation/Enable)
      
      // Setup Control Outs
      adspi_wr(0x035,0x00);	// Ctrl Out index
      adspi_wr(0x036,0xFF);	// Ctrl Out [7:0] output enable
      
      // Setup GPO
      adspi_wr(0x03A,0x27);	// Set number of REFCLK cycles for 1us delay timer
      adspi_wr(0x020,0x00);	// GPO Auto Enable Setup in RX and TX
      adspi_wr(0x027,0x03);	// GPO Manual and GPO auto value in ALERT
      adspi_wr(0x028,0x00);	// GPO_0 RX Delay
      adspi_wr(0x029,0x00);	// GPO_1 RX Delay
      adspi_wr(0x02A,0x00);	// GPO_2 RX Delay
      adspi_wr(0x02B,0x00);	// GPO_3 RX Delay
      adspi_wr(0x02C,0x00);	// GPO_0 TX Delay
      adspi_wr(0x02D,0x00);	// GPO_1 TX Delay
      adspi_wr(0x02E,0x00);	// GPO_2 TX Delay
      adspi_wr(0x02F,0x00);	// GPO_3 TX Delay
      
      // Setup RF PLL non-frequency-dependent registers
      adspi_wr(0x261,0x00);	// Set Rx LO Power mode
      adspi_wr(0x2A1,0x00);	// Set Tx LO Power mode
      adspi_wr(0x248,0x0B);	// Enable Rx VCO LDO
      adspi_wr(0x288,0x0B);	// Enable Tx VCO LDO
      adspi_wr(0x246,0x02);	// Set VCO Power down TCF bits
      adspi_wr(0x286,0x02);	// Set VCO Power down TCF bits
      adspi_wr(0x249,0x8E);	// Set VCO cal length
      adspi_wr(0x289,0x8E);	// Set VCO cal length
      adspi_wr(0x23B,0x80);	// Enable Rx VCO cal
      adspi_wr(0x27B,0x80);	// Enable Tx VCO cal
      adspi_wr(0x243,0x0D);	// Set Rx prescaler bias
      adspi_wr(0x283,0x0D);	// Set Tx prescaler bias
      adspi_wr(0x23D,0x00);	// Clear Half VCO cal clock setting
      adspi_wr(0x27D,0x00);	// Clear Half VCO cal clock setting
      
      adspi_wr(0x015,0x04);	// Set Dual Synth mode bit
      adspi_wr(0x014,0x0D);	// Set Force ALERT State bit
      adspi_wr(0x013,0x01);	// Set ENSM FDD mode
      //waits 1 ms
      ryan_printf("\n\r --- AD9361 testing : waits 1 ms --- \n\r");
      
      adspi_wr(0x23D,0x04);	// Start RX CP cal
      
      do {
          adspi_rd(0x244, &rd_data);
          rd_data = (rd_data >> 7) & 0x1;
      }while(rd_data==0x0);
      
      adspi_wr(0x27D,0x04);	// Start TX CP cal
      
      do {
          adspi_rd(0x284, &rd_data);
          rd_data = (rd_data >> 7) & 0x1;
      }while(rd_data==0x0);
      
      adspi_wr(0x23D,0x00);	// Disable RX CP Calibration since the CP Cal start bit is not self-clearing.  Only important if the script is run again without restting the DUT
      adspi_wr(0x27D,0x00);	// Disable TX CP Calibration since the CP Cal start bit is not self-clearing.  Only important if the script is run again without restting the DUT
      
      // FDD RX,TX Synth Frequency: 2400.000000,2500.000000 MHz
      // Setup Rx Frequency-Dependent Syntheisizer Registers
      adspi_wr(0x23A,0x4A);	// Set VCO Output level[3:0]
      adspi_wr(0x239,0xC0);	// Set Init ALC Value[3:0] and VCO Varactor[3:0]
      adspi_wr(0x242,0x0D);	// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
      adspi_wr(0x238,0x68);	// Set VCO Cal Offset[3:0]
      adspi_wr(0x245,0x00);	// Set VCO Cal Ref Tcf[2:0]
      adspi_wr(0x251,0x09);	// Set VCO Varactor Reference[3:0]
      adspi_wr(0x250,0x70);	// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
      adspi_wr(0x23B,0x91);	// Set Synth Loop Filter charge pump current (Icp)
      adspi_wr(0x23E,0xD4);	// Set Synth Loop Filter C2 and C1
      adspi_wr(0x23F,0xDF);	// Set Synth Loop Filter  R1 and C3
      adspi_wr(0x240,0x09);	// Set Synth Loop Filter R3
      
      // Setup Tx Frequency-Dependent Syntheisizer Registers
      adspi_wr(0x27A,0x4A);	// Set VCO Output level[3:0]
      adspi_wr(0x279,0xC0);	// Set Init ALC Value[3:0] and VCO Varactor[3:0]
      adspi_wr(0x282,0x0D);	// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
      adspi_wr(0x278,0x70);	// Set VCO Cal Offset[3:0]
      adspi_wr(0x285,0x00);	// Set VCO Cal Ref Tcf[2:0]
      adspi_wr(0x291,0x09);	// Set VCO Varactor Reference[3:0]
      adspi_wr(0x290,0x70);	// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
      adspi_wr(0x27B,0x8F);	// Set Synth Loop Filter charge pump current (Icp)
      adspi_wr(0x27E,0xD4);	// Set Synth Loop Filter C2 and C1
      adspi_wr(0x27F,0xDF);	// Set Synth Loop Filter  R1 and C3
      adspi_wr(0x280,0x09);	// Set Synth Loop Filter R3
      
      // Write Rx and Tx Frequency
      adspi_wr(0x233,0x00);	// Write Rx Synth Fractional Freq Word[7:0]
      adspi_wr(0x234,0x00);	// Write Rx Synth Fractional Freq Word[15:8]
      adspi_wr(0x235,0x00);	// Write Rx Synth Fractional Freq Word[22:16]
      adspi_wr(0x232,0x00);	// Write Rx Synth Integer Freq Word[10:8]
      adspi_wr(0x231,0x78);	// Write Rx Synth Integer Freq Word[7:0]
      adspi_wr(0x005,0x11);	// Set LO divider setting
      adspi_wr(0x273,0x00);	// Write Tx Synth Fractional Freq Word[7:0]
      adspi_wr(0x274,0x00);	// Write Tx Synth Fractional Freq Word[15:8]
      adspi_wr(0x275,0x00);	// Write Tx Synth Fractional Freq Word[22:16]
      adspi_wr(0x272,0x00);	// Write Tx Synth Integer Freq Word[10:8]
      adspi_wr(0x271,0x7D);	// Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
      adspi_wr(0x005,0x11);	// Set LO divider setting
      
      do {
          adspi_rd(0x247, &rd_data);
          rd_data = (rd_data >> 1) & 0x1;
      }while(rd_data==0x0);
      
      do {
          adspi_rd(0x287, &rd_data);
          rd_data = (rd_data >> 1) & 0x1;
      }while(rd_data==0x0);
      
      // Program Mixer GM Sub-table
      adspi_wr(0x13F,0x02);	// Start Clock
      adspi_wr(0x138,0x0F);	// Addr Table Index
      adspi_wr(0x139,0x78);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x00);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x0E);	// Addr Table Index
      adspi_wr(0x139,0x74);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x0D);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x0D);	// Addr Table Index
      adspi_wr(0x139,0x70);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x15);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x0C);	// Addr Table Index
      adspi_wr(0x139,0x6C);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x1B);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x0B);	// Addr Table Index
      adspi_wr(0x139,0x68);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x21);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x0A);	// Addr Table Index
      adspi_wr(0x139,0x64);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x25);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x09);	// Addr Table Index
      adspi_wr(0x139,0x60);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x29);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x08);	// Addr Table Index
      adspi_wr(0x139,0x5C);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x2C);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x07);	// Addr Table Index
      adspi_wr(0x139,0x58);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x2F);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x06);	// Addr Table Index
      adspi_wr(0x139,0x54);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x31);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x05);	// Addr Table Index
      adspi_wr(0x139,0x50);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x33);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x04);	// Addr Table Index
      adspi_wr(0x139,0x4C);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x34);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x03);	// Addr Table Index
      adspi_wr(0x139,0x48);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x35);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x02);	// Addr Table Index
      adspi_wr(0x139,0x30);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x3A);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x01);	// Addr Table Index
      adspi_wr(0x139,0x18);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x3D);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x138,0x00);	// Addr Table Index
      adspi_wr(0x139,0x00);	// Gain
      adspi_wr(0x13A,0x00);	// Bias
      adspi_wr(0x13B,0x3E);	// GM
      adspi_wr(0x13F,0x06);	// Write Words
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x13F,0x02);	// Clear Write Bit
      adspi_wr(0x13C,0x00);	// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
      adspi_wr(0x13C,0x00);	// Delay ~1us (Dummy Write)
      adspi_wr(0x13F,0x00);	// Stop Clock
      
      
      // Program Rx Gain Tables
      // Check status by GPIO
      for (i=0x1E;i<0x1F;i++){  
    			adspi_wr(0x035,i);
    		  rdata = READ(ADSPICTRLADDR);
    			ryan_printf(" --- -> Control Output : 0x");
    			puthex((unsigned char) ((rdata >> 24) & 0xFF));
    			ryan_printf("\n\r");
    	}
    
      adspi_wr(0x137,0x1A);	// Start Gain Table Clock
      adspi_wr(0x130,0x00);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x01);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x02);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x03);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x01);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x04);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x02);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x05);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x03);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x06);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x04);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x07);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x05);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x08);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x03);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x09);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x04);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x0A);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x05);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x0B);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x06);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x0C);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x07);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x0D);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x08);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x0E);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x09);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x0F);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0A);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x10);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0B);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x11);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0C);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x12);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0D);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x13);	// Gain Table Index
      adspi_wr(0x131,0x01);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0E);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x14);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x09);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x15);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0A);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x16);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0B);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x17);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0C);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x18);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0D);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x19);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0E);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x1A);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x0F);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x1B);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x10);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x1C);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2B);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x1D);	// Gain Table Index
      adspi_wr(0x131,0x02);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2C);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x1E);	// Gain Table Index
      adspi_wr(0x131,0x04);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x27);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x1F);	// Gain Table Index
      adspi_wr(0x131,0x04);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x28);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x20);	// Gain Table Index
      adspi_wr(0x131,0x04);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x29);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x21);	// Gain Table Index
      adspi_wr(0x131,0x04);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2A);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x22);	// Gain Table Index
      adspi_wr(0x131,0x04);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2B);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x23);	// Gain Table Index
      adspi_wr(0x131,0x24);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x21);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x24);	// Gain Table Index
      adspi_wr(0x131,0x24);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x22);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x25);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x20);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x26);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x21);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x27);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x22);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x28);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x23);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x29);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x24);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x2A);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x25);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x2B);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x26);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x2C);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x27);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x2D);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x28);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x2E);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x29);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x2F);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2A);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x30);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2B);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x31);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2C);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x32);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2D);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x33);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2E);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x34);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2F);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x35);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x30);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x36);	// Gain Table Index
      adspi_wr(0x131,0x44);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x31);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x37);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2E);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x38);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x2F);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x39);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x30);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x3A);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x31);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x3B);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x32);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x3C);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x33);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x3D);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x34);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x3E);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x35);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x3F);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x36);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x40);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x37);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x41);	// Gain Table Index
      adspi_wr(0x131,0x64);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x42);	// Gain Table Index
      adspi_wr(0x131,0x65);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x43);	// Gain Table Index
      adspi_wr(0x131,0x66);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x44);	// Gain Table Index
      adspi_wr(0x131,0x67);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x45);	// Gain Table Index
      adspi_wr(0x131,0x68);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x46);	// Gain Table Index
      adspi_wr(0x131,0x69);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x47);	// Gain Table Index
      adspi_wr(0x131,0x6A);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x48);	// Gain Table Index
      adspi_wr(0x131,0x6B);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x49);	// Gain Table Index
      adspi_wr(0x131,0x6C);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x4A);	// Gain Table Index
      adspi_wr(0x131,0x6D);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x4B);	// Gain Table Index
      adspi_wr(0x131,0x6E);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x4C);	// Gain Table Index
      adspi_wr(0x131,0x6F);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x38);	// TIA & LPF Word
      adspi_wr(0x133,0x20);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x4D);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x4E);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x4F);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x50);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x51);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x52);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x53);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x54);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x55);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x56);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x57);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x58);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x59);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x130,0x5A);	// Gain Table Index
      adspi_wr(0x131,0x00);	// Ext LNA, Int LNA, & Mixer Gain Word
      adspi_wr(0x132,0x00);	// TIA & LPF Word
      adspi_wr(0x133,0x00);	// DC Cal bit & Dig Gain Word
      adspi_wr(0x137,0x1E);	// Write Words
      adspi_wr(0x134,0x00);	// Dummy Write to delay 3 ADCCLK/16 cycles
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x137,0x1A);	// Clear Write Bit
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x134,0x00);	// Dummy Write to delay ~1us
      adspi_wr(0x137,0x00);	// Stop Gain Table Clock
    	
      // Setup Rx Manual Gain Registers
      // Check status by GPIO
      for (i=0x1E;i<0x1F;i++){  
    			adspi_wr(0x035,i);
    		  rdata = READ(ADSPICTRLADDR);
    			ryan_printf(" --- -> Control Output : 0x");
    			puthex((unsigned char) ((rdata >> 24) & 0xFF));
    			ryan_printf("\n\r");
    	}
      adspi_wr(0x0FA,0xE0);	// Gain Control Mode Select
      adspi_wr(0x0FB,0x08);	// Table, Digital Gain, Man Gain Ctrl
      adspi_wr(0x0FC,0x23);	// Incr Step Size, ADC Overrange Size
      adspi_wr(0x0FD,0x4C);	// Max Full/LMT Gain Table Index
      adspi_wr(0x0FE,0x44);	// Decr Step Size, Peak Overload Time
      adspi_wr(0x100,0x6F);	// Max Digital Gain
      adspi_wr(0x104,0x2F);	// ADC Small Overload Threshold
      adspi_wr(0x105,0x3A);	// ADC Large Overload Threshold
      adspi_wr(0x107,0x2B);	// Small LMT Overload Threshold
      adspi_wr(0x108,0x31);	// Large LMT Overload Threshold
      adspi_wr(0x109,0x4C);	// Rx1 Full/LMT Gain Index
      adspi_wr(0x10A,0xF8);	// Rx1 LPF Gain Index
      adspi_wr(0x10B,0x00);	// Rx1 Digital Gain Index
      adspi_wr(0x10C,0x4C);	// Rx2 Full/LMT Gain Index
      adspi_wr(0x10D,0x18);	// Rx2 LPF Gain Index
      adspi_wr(0x10E,0x00);	// Rx2 Digital Gain Index
      adspi_wr(0x114,0x30);	// Low Power Threshold
      adspi_wr(0x11A,0x1C);	// Initial LMT Gain Limit
      adspi_wr(0x081,0x00);	// Tx Symbol Gain Control
      
      // RX Baseband Filter Tuning
      // Check status by GPIO
      for (i=0x1E;i<0x1F;i++){  
    			adspi_wr(0x035,i);
    		  rdata = READ(ADSPICTRLADDR);
    			ryan_printf(" --- -> Control Output : 0x");
    			puthex((unsigned char) ((rdata >> 24) & 0xFF));
    			ryan_printf("\n\r");
    	}
      adspi_wr(0x1FB,0x01);	// RX Freq Corner (MHz)
      adspi_wr(0x1FC,0x00);	// RX Freq Corner (Khz)
      adspi_wr(0x1F8,0x3D);	// Rx BBF Tune Divider[7:0]
      adspi_wr(0x1F9,0x1E);	// RX BBF Tune Divider[8]
      
      adspi_wr(0x1D5,0x3F);	// Set Rx Mix LO CM
      adspi_wr(0x1C0,0x03);	// Set GM common mode
      adspi_wr(0x1E2,0x02);	// Enable Rx1 Filter Tuner 
      adspi_wr(0x1E3,0x02);	// Enable Rx2 Filter Tuner 
      adspi_wr(0x016,0x80);	// Start RX Filter Tune
      
      do {
          adspi_rd(0x016, &rd_data);
          rd_data = (rd_data >> 7) & 0x1;
      }while(rd_data);
      
      adspi_wr(0x1E2,0x03);	// Disable Rx Filter Tuner (Rx1)
      adspi_wr(0x1E3,0x03);	// Disable Rx Filter Tuner (Rx2)
      
      // TX Baseband Filter Tuning
      adspi_wr(0x0D6,0x35);	// TX BBF Tune Divider[7:0]
      adspi_wr(0x0D7,0x1E);	// TX BBF Tune Divider[8]
      
      adspi_wr(0x0CA,0x22);	// Enable Tx Filter Tuner
      adspi_wr(0x016,0x40);	// Start Tx Filter Tune
      
      do {
          adspi_rd(0x016, &rd_data);
          rd_data = (rd_data >> 6) & 0x1;
      }while(rd_data);
      
      adspi_wr(0x0CA,0x26);	// Disable Tx Filter Tuner (Both Channels)
      
      // RX TIA Setup
      adspi_rd(0x1EB, &rd_data);	// Read RXBBF C3(MSB)
      adspi_rd(0x1EC, &rd_data);	// Read RXBBF C3(LSB)
      adspi_rd(0x1E6, &rd_data);	// Read RXBBF R2346
      adspi_wr(0x1DB,0xE0);	// Set TIA selcc[2:0]
      adspi_wr(0x1DD,0x37);	// Set RX TIA1 C MSB[6:0]
      adspi_wr(0x1DF,0x37);	// Set RX TIA2 C MSB[6:0]
      adspi_wr(0x1DC,0x40);	// Set RX TIA1 C LSB[5:0]
      adspi_wr(0x1DE,0x40);	// Set RX TIA2 C LSB[5:0]
      
      // TX Secondary Filter
      adspi_wr(0x0D2,0x1C);	// TX Secondary Filter PDF Cap cal[5:0]
      adspi_wr(0x0D1,0x01);	// TX Secondary Filter PDF Res cal[3:0]
      adspi_wr(0x0D0,0x59);	// Pdampbias 
      
      // ADC Setup
      adspi_rd(0x1EB, &rd_data);	// Read RxBBF C3 MSB after calibration
      adspi_rd(0x1EC, &rd_data);	// Read RxBBF C3 LSB after calibration
      adspi_rd(0x1E6, &rd_data);	// Read RxBBF R3 after calibration
    
      // ADC=48MHz
      adspi_wr(0x200,0x00);
      adspi_wr(0x201,0x00);
      adspi_wr(0x202,0x00);
      adspi_wr(0x203,0x24);
      adspi_wr(0x204,0x24);
      adspi_wr(0x205,0x00);
      adspi_wr(0x206,0x00);
      adspi_wr(0x207,0x2A);
      adspi_wr(0x208,0x8F);
      adspi_wr(0x209,0x20);
      adspi_wr(0x20A,0x29);
      adspi_wr(0x20B,0x91);
      adspi_wr(0x20C,0x2A);
      adspi_wr(0x20D,0x8D);
      adspi_wr(0x20E,0x15);
      adspi_wr(0x20F,0x2B);
      adspi_wr(0x210,0x2D);
      adspi_wr(0x211,0x2B);
      adspi_wr(0x212,0x28);
      adspi_wr(0x213,0x29);
      adspi_wr(0x214,0x28);
      adspi_wr(0x215,0x29);
      adspi_wr(0x216,0x2A);
      adspi_wr(0x217,0x29);
      adspi_wr(0x218,0x2E);
      adspi_wr(0x219,0x84);
      adspi_wr(0x21A,0x09);
      adspi_wr(0x21B,0x08);
      adspi_wr(0x21C,0x84);
      adspi_wr(0x21D,0x09);
      adspi_wr(0x21E,0x08);
      adspi_wr(0x21F,0x84);
      adspi_wr(0x220,0x09);
      adspi_wr(0x221,0x11);
      adspi_wr(0x222,0x11);
      adspi_wr(0x223,0x40);
      adspi_wr(0x224,0x40);
      adspi_wr(0x225,0x2C);
      adspi_wr(0x226,0x00);
      adspi_wr(0x227,0x00);
    
    
      //************************************************************
      // Setup and Run BB DC and RF DC Offset Calibrations
      //************************************************************
      adspi_wr(0x193,0x3F);
      adspi_wr(0x190,0x0F);	// Set BBDC tracking shift M value, only applies when BB DC tracking enabled
      adspi_wr(0x194,0x01);	// BBDC Cal setting
      adspi_wr(0x016,0x01);	// Start BBDC offset cal
    
      do {
          adspi_rd(0x016, &rd_data);
          rd_data = (rd_data) & 0x1;
      }while(rd_data);
    
    	getensm();
    	
      // Check status by GPIO
      for (i=0x1E;i<0x1F;i++){  
    			adspi_wr(0x035,i);
    		  rdata = READ(ADSPICTRLADDR);
    			ryan_printf(" --- -> Control Output : 0x");
    			puthex((unsigned char) ((rdata >> 24) & 0xFF));
    			ryan_printf("\n\r");
    	}
    	
      adspi_wr(0x185,0x50);//0x20);	// Set RF DC offset Wait Count
      adspi_wr(0x186,0xBA);//0x32);	// Set RF DC Offset Count[7:0]
      adspi_wr(0x187,0x24);//24);	// Settings for RF DC cal
      adspi_wr(0x18B,0x83);//0x83);	// Settings for RF DC cal
      adspi_wr(0x188,0x05);	// Settings for RF DC cal
      adspi_wr(0x189,0x30);	// Settings for RF DC cal
      // Check status by GPIO
      for (i=0x1E;i<0x1F;i++){  
    			adspi_wr(0x035,i);
    		  rdata = READ(ADSPICTRLADDR);
    			ryan_printf(" --- -> Control Output : 0x");
    			puthex((unsigned char) ((rdata >> 24) & 0xFF));
    			ryan_printf("\n\r");
    	}
      adspi_wr(0x016,0x02);	// Start RFDC offset cal
      
      do {
    		for (i=0x0;i<0x20;i++){  
    			adspi_wr(0x035,i);
    		  rdata = READ(ADSPICTRLADDR);
    			ryan_printf(" --- -> Control Output : 0x");
    			puthex((unsigned char) ((rdata >> 24) & 0xFF));
    			ryan_printf("\n\r");
    		}
        adspi_rd(0x016, &rd_data);
        rd_data = (rd_data >> 1) & 0x1;
      }while(rd_data);
    
    
      // Tx Quadrature Calibration Settings
      adspi_rd(0x0A3, &rd_data);	// Masked Read:  Read lower 6 bits, overwrite [7:6] below
      adspi_wr(0x0A0,0x15);	// Set TxQuadcal NCO frequency
      adspi_wr(0x0A3,0x00);	// Set TxQuadcal NCO frequency (Only update bits [7:6])
      adspi_wr(0x0A1,0x7B);	// Tx Quad Cal Configuration, Phase and Gain Cal Enable
      adspi_wr(0x0A9,0xFF);	// Set Tx Quad Cal Count
      adspi_wr(0x0A2,0x7F);	// Set Tx Quad Cal Kexp
      adspi_wr(0x0A5,0x01);	// Set Tx Quad Cal Magnitude Threshhold
      adspi_wr(0x0A6,0x01);	// Set Tx Quad Cal Magnitude Threshhold
      adspi_wr(0x0AA,0x25);	// Set Tx Quad Cal Gain Table index
      adspi_wr(0x0A4,0xF0);	// Set Tx Quad Cal Settle Count
      adspi_wr(0x0AE,0x00);	// Set Tx Quad Cal LPF Gain index incase Split table mode used
      
      adspi_wr(0x169,0xC0);	// Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
      adspi_wr(0x016,0x10);	// Start Tx Quad cal
      
      do {
          adspi_rd(0x016, &rd_data);
          rd_data = (rd_data >> 4) & 0x1;
      }while(rd_data);
      
      adspi_wr(0x16A,0x75);	// Set Kexp Phase
      adspi_wr(0x16B,0x95);	// Set Kexp Amplitude & Prevent Positive Gain Bit
      adspi_wr(0x169,0xCF);	// Enable Rx Quadrature Calibration Tracking
      adspi_wr(0x18B,0xAD);	// Enable BB and RF DC Tracking Calibrations
      adspi_wr(0x012,0x42);	// Cals done, Set PPORT Config
      adspi_wr(0x013,0x01);	// Set ENSM FDD/TDD bit
      adspi_wr(0x015,0x84);	// Set Dual Synth Mode, FDD External Control bits properly
      
      // Set Tx Attenuation
      adspi_wr(0x073,0x28);
      adspi_wr(0x074,0x00);
      adspi_wr(0x075,0x28);
      adspi_wr(0x076,0x00);
    
      getensm();
    	
    
      // RSSI and Power Measurement
      adspi_wr(0x150,0x0E);	// RSSI Measurement Duration 0, 1
      adspi_wr(0x151,0x00);	// RSSI Measurement Duration 2, 3
      adspi_wr(0x152,0xFF);	// RSSI Weighted Multiplier 0
      adspi_wr(0x153,0x00);	// RSSI Weighted Multiplier 1
      adspi_wr(0x154,0x00);	// RSSI Weighted Multiplier 2
      adspi_wr(0x155,0x00);	// RSSI Weighted Multiplier 3
      adspi_wr(0x156,0x00);	// RSSI Delay
      adspi_wr(0x157,0x00);	// RSSI Wait
      adspi_wr(0x158,0x0D);	// RSSI Mode Select
      adspi_wr(0x15C,0x67);	// Power Measurement Duration
    	
    	getensm();
    	//ENTER ALERT
    	//adspi_wr(0x014,0x07);
    	//getensm();
    	//ENTER FDD
    	adspi_wr(0x014,0x23);
    	//wait 1ms
    	ryan_printf(" --- -> Wait 10(ms) to enter ENSM FDD state ...\n\r");
    	getensm();
    	
    	//RX Enable
    	setenable();
    	

  • We donot support using register writes for configuring our chip. Please use linux or no -os drivers.

    Also, share the profile that you are using in linux format so taht we can load it to IIO and then check.

  • hello ,  i meet same question , could you  share your solution?Thanks