The issue I am having is that I designed new FIR filters for the AD9361 to take advantage of up to all 128 coefficients in the filter.

The old filters have been working fine for most BWs but the 56 Mhz specifically I needed to use all the coefficients available.

I changed the tx interpolation value to 2 and rx decimation to 2 as well per the user manual for 128 taps, but they aren’t working for most of the bandwidth filters.

Tx FIR The first digital filter in the Tx signal path is a programmable polyphase FIR filter. The Tx FIR filter can also interpolate by a factor of 1, 2, or 4, or it can be bypassed if not needed. This filter is controlled in the ad9361_set_tx_fir_config. The filter taps are stored in 16-bit twos complement format, and the number of taps is configurable between a minimum of 16 taps and a maximum of 128 taps in groups of 16. The Tx FIR also has a programmable gain setting of 0 dB or −6 dB. Each coefficient is stored in two registers as a 16-bit number.

The Tx FIR uses DAC_CLK (Tx DAC sample clock) as its sample clock. DAC_CLK is either set equal to ADC_CLK or is set to ADC_CLK/2. The Tx FIR calculates 16 taps per clock cycle. This limits the number of available taps to the ratio of DAC_CLK to the input data rate multiplied by 16. For example, if the input data rate is 25 MHz and DAC_CLK is 100 MHz, then the ratio of DAC_CLK to the input data rate is 100/25 or 4. In this scenario, the total number of taps available is 64.

Another limitation is the memory inside the filter. The total number of operations that can be performed is limited to 64 per clock cycle. This means that the number of taps available is limited to 64 if the interpolation factor is set to 1. If an interpolation rate greater than 1 is used, then the memory space can be utilized to include more taps. Table 15 lists the allowable number of taps for each interpolation rate.

I thought I might have found the solution in the datasheet yesterday:

Currently the filters have these clocks and this is the tx 56 Mhz filter generated from the MATLAB application:

AD9361_TXFIRConfig rx2tx_fpass_28_fstop_30p72_tx_fir_config = { 3, // tx 0, // tx_gain 2, // tx_int {80,255,335,199,-100,-182,1,173,39,-157,-83,151,120,-137,-164,119,207,-88,-252,47,293,10,-329,-79,354,162,-366,-257,359,362,-330,-473,276,587,-194,-699,79,803,70,-893,-255,960,479,-997,-743,993,1050,-935,-1403,808,1810,-587,-2283,233,2845,323,-3548,-1228,4505,2840,-6123,-6617,10581,30449,30449,10581,-6617,-6123,2840,4505,-1228,-3548,323,2845,233,-2283,-587,1810,808,-1403,-935,1050,993,-743,-997,479,960,-255,-893,70,803,79,-699,-194,587,276,-473,-330,362,359,-257,-366,162,354,-79,-329,10,293,47,-252,-88,207,119,-164,-137,120,151,-83,-157,39,173,1,-182,-100,199,335,255,80}, // tx_coef[128] 128, // tx_coef_size {983040000,491520000,122880000,122880000,122880000,61440000}, // tx_path_clks[6] 33889517 // tx_bandwidth };

These are the clock configurations:

ADC/DAC Sample Clock Rate = 61.44 MHz

TX/RX FIR Clock = HB1 = HB2 = HB3 = 122.88 MHz ADC/DAC Clock = 245.76 MHz PLL Clock Rate = 983.04 MHz

This is what is expected based off the matlab AD FIR design application:

DAC is 24576

Input data rate is 6144

Using the ratio from the text:

24576/6144 = 4 * 16 = 64 taps

So I tried doubling the dac rate to get a ratio of 8 ( 8*16 = 128), however in testing the AD9361_init failed to work and got stuck.

I’m kind of back to the drawing board at this point. Any issues that stick out or is it an API issue?

Can someone explain any big changes that need to be made between going from tx_int 1 -> 2 and 64 -> 128 coefficients