I was wondering what the recommended bypassing is for the VDD_RX_SYNTH and VDD_TX_SYNTH rails as well as the other +1.3V rails. On the FMCOMMS3 board it seems like for those only a 1uF and 0.01uF cap are needed as close to each ball (J3/K3) as possible. In other reference designs, it shows a 10uF and 0.01uF. What is the recommended bypassing scheme? Is there an application note that describes in detail what size capacitors/capacitance is needed for each of the balls?
Apart from FMCOMMS 3 board, which board's reference design are you referring to?
I can't seem to find the original reference design with the 10uF and 0.01uF but I know there were some which had this bypass scheme which is why the highest capacitance was put on the board that we designed. Regardless, what is the recommended bypassing scheme? Is there an application note that describes in detail what size capacitors/capacitance is needed for each of the balls? Would 1uF and 0.01uF capacitance be sufficient for those two lines?
You can follow the FMCOMMS 3 reference design. The capacitors are sufficient for those two lines. A separate app note is not there.
Thank you. Do you have any idea of which past reference design used a 10uF value and if so why it changed to the 1uF? The previous engineer on the board I'm designing used a reference board from ADI but I can't seem to find where he found that information.
You may go with 10UF , 1UF and .01UF and as per performance and impact seen on custom board , you can populate the required capacitors. Recommendation is to go with all three.
Power supply decaps depends on the board layout and other digital parts that are there on same board as well.