I have a question about setting AD9361 clock rates for TX/RX signal paths and maximum clock rates allowed. From this link I read that maximum clock rate should never exceed 640MHz. However when I look at the ADI No-OS source code in github I find a line where clock rate is more than 900MHz (here, lines 113 and 114). Also in the same source code little bit down below the structures AD9361_TXFIRConfig and AD9361_RXFIRConfig are defined with all clock rates ste to zero (here, lines 338, 363). Why is that and what kind of an effect does this have?
Please refer below post,
you can replace the original configurations with…
I've moved your post to the correct forum.
The first numbers are for the PLL not the converters. The PLL goes through dividers to the ADCs and DACs which have max rates 640 MHz and 320 MHz respectively. PLL max is 1.4 GHz.
Okay, so the first clock is for setting the PLL rate and the other values are as according to the schematic in the first link that I posted?
What about when setting all those rates to zero in the AD9361_RXFIRConfig function for example? Why is this so?
you can replace the original configurations with yours. However, in your situation, when you need to also change the sampling rate, you should use the ad9361_trx_load_enable_fir() API - it will enable the filters simultaneously and it will load the coefficients and the frequencies information too.
In our example we didn't change the frequencies, so calling ad9361_set_tx/rx_fir_config() and ad9361_set_tx/rx_fir_en_dis() was enough.