How to control internal ADC/DAC buffer in AD9361

let me clarify my question in simpler words. 
Is the adc and dac path latency deterministic every time ad9361 is powered on? And if it’s not how could you make it fixed every time you power it on? 

The latency through the chain is fixed for a fixed configuration , If configuration changes we have FIR filters and when that changes the latency changes. Please refer User Guide UG-570 section on Digital Tx Block Delay. 

To send data at same time you need to provide data at interface at same time.

What is your application ? If you are looking for Phase synchronization please refer below link.

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/multi-chip-sync 

Thanks Vinod

Assuming a fixed configuration, is there any other source of latency in Tx path ? In the past we tested DAC path with fixed configuration and on different power up cycles the latency is fixed but it's different.

In our application we don't send two stream of data from two TX ports to utilized multi chip synch mechanism. However it's extremely important for us to know the exact latency from when we drive DAC input to the RF output. We have observed that such latency is fixed, but slightly changes at every power up cycle.

Sean

Thanks Vinod

Assuming a fixed configuration, is there any other source of latency in Tx path ? In the past we tested DAC path with fixed configuration and on different power up cycles the latency is fixed but it's different.

In our application we don't send two stream of data from two TX ports to utilized multi chip synch mechanism. However it's extremely important for us to know the exact latency from when we drive DAC input to the RF output. We have observed that such latency is fixed, but slightly changes at every power up cycle.

Sean

 For a fixed configuration and fixed frequency, the delay will remain fixed. But with every power up, the way the LO signal(phase of the signal)mixes with the input signal will vary even though the frequency of the LO is the same. So you can expect a  difference in delay from the previous power up.

Thanks @srimoyi  for clarification. That's exactly the reason, but is there anyway to start from a known LO phase?

There can be a slight variation in path delay with every power up and you have to calibrate for this change in delay  in your baseband.

srimoyisure, but the problem is that there are variations both on the TX and RX side. The questions is how to isolate the TX variance with RX delay path?

You could loopback TX to RX and measure the delay in the baseband, but that has the delay path of your RX side. This method you cannot just measure the delay path on TX side.

In my application I need to know the latency of TX side only! 

You can loopback TX1 to both RX1 and RX2 within the same chip and then calibrate for that difference as mentioned in the below link between two boards:

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/multi-chip-sync?s[]=mcs#when_it_s_needed_to_go_through_a_mcs_sequence