How to control internal ADC/DAC buffer in AD9361

Hi

I assume there's a circular buffer inside ad9361 chip before ADC/DAC converter and depending on power up time they could have any random position before we drive actual data to DAC or ADC. This is a problem for my application where I need to know a deterministic delay between transmit DAC on one AD9361 and ADC on another ad9361 .

To clarify my problem I set an example. Suppose I have 2 ad9361s, one is Tx and one is Rx. At time T0 I turn on ad9361_1 and some time later at T1 I turn on ad9361_2. Yet I have not sent any data, so I assume DAC buffer is circulating around and sending out noise. I suppose buffer size is 256 symbols. Imagine at T2 I start to drive ad9361 DAC and at this time buffer is at location 32. my first data sits at location 0 of the buffer so it needs to circle 256-32 to reach to my first data to send. So technically I now have delay of 224 on my DAC side and the same scenario could happen at ad9361_2 where the ADC buffer is circulating before it could receive the first data. 

With this example I hope I conveyed that we could have a deterministic delay between 2 operating ADC/DAC. Now I wonder if I could remove this deterministic delay by maybe resetting DAC/ADC buffers? or any other solutions. Or maybe there's no such buffer before or after ADC/DAC in 9361? 

Please let me know your thoughts and let me know if you have any questions.

Thanks,

Sean   

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  • Thanks

    Assuming a fixed configuration, is there any other source of latency in Tx path ? In the past we tested DAC path with fixed configuration and on different power up cycles the latency is fixed but it's different.

    In our application we don't send two stream of data from two TX ports to utilized multi chip synch mechanism. However it's extremely important for us to know the exact latency from when we drive DAC input to the RF output. We have observed that such latency is fixed, but slightly changes at every power up cycle.

    Sean

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