post on behalf on a customer ....
"I am using the AD9361 for precise timing synchronization.
I am in the Tx calibration phase, I got an issue with the way where data are sampled at the input of Tx Channel block inside the front-end.
I use the digital interface with 1R1T mode and I observe an arbitrary delay with a difference of 1 DATA_CLK period on the RF output each time I reconfigure the PLL inside the front-end.
I synchronise all of my clock inside my BB FPGA on the RX_FRAME signal."
Is they exist a way to fix this delay or to measure it ?
I am agree with your for the LO generation, but the delay observed on my RF output between two PLL reconfiguration is 1 DATA_CLK (or 1 FB_CLK) period, not 1 LO period.
The point not clear for me is how the TX data send by the BB FPGA are synchronized inside the AD9361. Even if the FB_CLK output of the FPGA is generated using DATA_CLK input (in my case I use a loop back), the phase relationship can be different and according to the UG 570, this is not a problem. It imply the use of a synchronisation mechanism before the input of the Tx FIR because the Tx function inside the AD9361 use clocks derivated of the same source than DATA_CLK (without relationship with the FB_CLK).
couple of things to check.
Digital timing verification : https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/interface_timing_validation?s=interface&s=tuning
Read back the register 0x011[D0:D1] : Delay Rx Data[1:0] :These bits set the delay of the Rx data relative to Rx frame, measured in ½ DATA_CLK cycles for DDR and full DATA_CLK cycles for SDR.)