AD9361 and inside Timing issues and query


post on behalf on a customer ....

"I am using the AD9361 for precise timing synchronization.

I am in the Tx calibration phase, I got an issue with the way where data are sampled at the input of Tx Channel block inside the front-end.

I use the digital interface with 1R1T mode and I observe an arbitrary delay with a difference of 1 DATA_CLK period on the RF output each time I reconfigure the PLL inside the front-end.

I synchronise all of my clock inside my BB FPGA on the RX_FRAME signal."


Is they exist a way to fix this delay or to measure it ?



Parents Reply Children
  • Hi, 

    According to me, the issue I got comes from the clock domain change between the digital interface and the Tx channel. Is it possible to clarify the timing between data from the digital interface, sampled inside the BB FPGA and data sampled by the AD9361 at the input of the Tx FIR? 

    According to your previous answers to a similar issue :

    The initialisation of the PLL are random (not for the LO, I well understand this one is not synchronised) ? 

    I observed also this issue when I test the AD9361 with the digital loop back feature, I solved the measurement issue by synchronising the TX_FRAME on the RX_FRAME signal. Now I think this synchronisation just mask the problem but does not solve it.

    I check also the MGC features but I think this feature guarantees the same delay between two boards but not the same delay between two initialisation.

    The test I made to find this issue is the following :

    I use a pattern to transmit a signal, a pulse is generated at 100the beginning of this pattern, this pulse is connected to an output of the FPGA and monitored using a scope.

    On the other way, this patten is send to the digital interface, my TX_FRAME is synchronised on the RX_FRAME (it guarantees a fixed delay between two initialisation) and the output of the AD9361 is connected to the same scope. 

    I tune my trigger on the reference pulse and set the scope in accumulation mode. 

    I measure the time between the reference pulse and the middle of the carrier inversion caused by my pattern. 

    The delay observed over several test vary of 1 DATA_CLK period.

    The same issue is observed here :



  • 0
    •  Analog Employees 
    on Nov 13, 2019 7:14 AM over 1 year ago in reply to AMERMET39

    The phase with which the LO comes up with every power up might be different even though the frequency remains the same between power up. So with every power up, the delay between the input and the output signal may vary.

    AD9361 supports only baseband sync and not RFPLL synchronization. MCS in this chip, makes sure that all the sampling and data_clks are generated from a common ref clock. So with every power up, all the digital clocks are aligned w.r.t a common source and hence the delay of all the clcoks w.r.t the ref_clk remains the same with every power up.

  • I am agree with your for the LO generation, but the delay observed on my RF output between two PLL reconfiguration is 1 DATA_CLK (or 1 FB_CLK) period, not 1 LO period.

    The point not clear for me is how the TX data send by the BB FPGA are synchronized inside the AD9361. Even if the FB_CLK output of the FPGA is generated using DATA_CLK input (in my case I use a loop back), the phase relationship can be different and according to the UG 570, this is not a problem. It imply the use of a synchronisation mechanism before the input of the Tx FIR because the Tx function inside the AD9361 use clocks derivated of the same source than DATA_CLK (without relationship with the FB_CLK).

  • 0
    •  Analog Employees 
    on Nov 22, 2019 8:58 AM over 1 year ago in reply to AMERMET39

    couple of things to check.

    Digital timing verification :[]=interface&s[]=tuning

    Read back the register 0x011[D0:D1] : Delay Rx Data[1:0] :These bits set the delay of the Rx data relative to Rx frame, measured in ½ DATA_CLK cycles for DDR and full DATA_CLK cycles for SDR.)