AD9361 and inside Timing issues and query

Hello,

post on behalf on a customer ....

"I am using the AD9361 for precise timing synchronization.

I am in the Tx calibration phase, I got an issue with the way where data are sampled at the input of Tx Channel block inside the front-end.

I use the digital interface with 1R1T mode and I observe an arbitrary delay with a difference of 1 DATA_CLK period on the RF output each time I reconfigure the PLL inside the front-end.

I synchronise all of my clock inside my BB FPGA on the RX_FRAME signal."

 

Is they exist a way to fix this delay or to measure it ?

Regards

Ching