I need some clarification about the max data sampling rate in a 2R configuration for the LVDS mode.
The max data clock rate in LVDS mode is 245.76 MHz.. I understand that in this mode, the
IQ samples are transmitted on the dedicated P1 port in the following sequence :
I1msb, Q1msb, I1lsb, Q1lsb, I2msb, Q2msb, I2lsb, Q2lsb (figure 79 of UG 570).
I conclude that the max IQ sampling rate in LVDS mode is 245.76/8 = 30.72 MHz. and not 61.44 MHz.
Is that correct ?
What will be the maximum RF bandwith in this case ?
Oops ! I forgot we are in DDR mode so the max sampling rate is effectively 61.44 MHz...