In my design I have 4 axi_ad9361 IPs to connect to 4 chips. 2 of these chips will only have 1 receive channel. So, on these two chips I was going to set the 1r1t parameter to '1'.
axi_ad9361_0 - 2 receivers
axi_ad9361_1 - 1 receiver
axi_ad9361_2 - 2 receivers
axi_ad9361_3 - 1 receiver
Option 1: Can I connect l_clk from axi_ad9361_0 to the clk inputs on all 4 chips? Would I need to set the 1r1t parameter to 0 on all 4?
Option 2: Do I connect l_clk from axi_ad9361_0 to axi_ad9361_0 clk and axi_ad9361_2 clk and l_clk from axi_ad9361_1 to axi_ad9361_1 clk and axi_ad9361_3 clk? Will I need two util_clk_dividers and two separate fifos (one fifo for ad9361_0,2 and one fifo for ad9361_1,3)?
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