I'm studying the FMCOMMS5 schematics with a goal to design my custom PCB with two AD9361 chips for my FPGA board. I'm planning to use external LO to synchronize the RF parts of the chips.
I had a look at the schematics were necessary power supplies are generated for the fanout-buffer and PLL and have a question regarding that. On the schematics the 12V power rail is first converted to 6V power rail and then split and converted to 5V and 3V3. When I had a look at the AD7150ARDZ, which is used for generating the both 5V and 3V3 rails, spec, then it's specified to handle the voltages up to 16V. So why is there a need for the additional buck regulator before that to take the voltage down to 6V?
I understand that both 5V and 3V3 rails need to be very clean, and low-noise. So is this the reason for this? And if so, then couldn't this be achieved with filtering and ferrite beads?
I had a look at the ADF5355 power supply requirements section and this circuit is actually the recommended one, so is the additional buck regulator maybe just because it was easier to design taking the reference schematic as the basis?
The reason why I'm asking this is because I won't be having the 12V power rail, but only a single 5V input power rail, from which all the other voltages are generated, so having a boost regulator just to bring it up to 6V and then back to 5V and 3V3 seems little bit in-efficient.
You can directly use your 5V supply source for connecting VDD_VCO_5V and derive VDD_EXT_LO_3P3 supply from your 5 volts source.
Please take care of the filtering and decoupling capacitors requirement for the circuits you are planning to load.