AD9361 multi-chip synchronization using the LO on FMCOMM5REVC


I would like to know if the FMCOMM5REVC evaluation board supports both external LO multi-chip synchronization as well as Internal LO/FPGA synchronization option? From the schematic I deduce that this evaluation board supports both options, as the same clock source is buffered and distributed to both chips LO nput, but I couldn't find any information from the documentation about this.

Is there maybe somewhere in AD documentation more detailed information about the external LO multi-chip synchronization, cause what I've found is pretty slim.

Also, I would appreciate if my post is not deleted this time without any feedback as to why. If I posted this in the wrong section, then please tell me or move it, but don't just delete this like my previous question regarding the same thing.

Thank you