AD9361 multi-chip synchronization using the LO on FMCOMM5REVC

Hi,

I would like to know if the FMCOMM5REVC evaluation board supports both external LO multi-chip synchronization as well as Internal LO/FPGA synchronization option? From the schematic I deduce that this evaluation board supports both options, as the same clock source is buffered and distributed to both chips LO nput, but I couldn't find any information from the documentation about this.

Is there maybe somewhere in AD documentation more detailed information about the external LO multi-chip synchronization, cause what I've found is pretty slim.

Also, I would appreciate if my post is not deleted this time without any feedback as to why. If I posted this in the wrong section, then please tell me or move it, but don't just delete this like my previous question regarding the same thing.

Thank you

  • 0
    •  Analog Employees 
    on Oct 23, 2019 6:27 AM over 1 year ago

    Both the chips do not have a common LO source, but FMCOMMS5 uses 4x4 external calibration option for RF phase synchronization. Refer to the below links for details:

    https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/hardware 

    https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/phase-sync

  • Thank you for the answer @srimoyi and thanks for the articles. I've actually read those already.

    Maybe I misunderstand the schematics, but when I look at the clock generation part, then to me it seems that there is one common clock source taken, synthesized to suitable frequency by ADF5355BCPZ and then fed into 1:2 clock fanout buffer which generates two identical (tskew <2ps) clocks for RX_EXT_LO_A and RX_EXT_LO_B nets. These nets are input to both AD9361 chips EXT_LO pins. 

    Ofcourse for this to work the 5355_RF_EN pin must be enabled by the carrier board.

    I've included a schematic explaining this. Can you please elaborate what to you mean when you say that these chips don't have a common LO?

  • 0
    •  Analog Employees 
    on Oct 24, 2019 1:12 PM over 1 year ago in reply to ronnu

    Yes. For external LO, a common LO source goes to both the two boards., but still external calibration is run to compensate for the phase changes and provide MCS. If using internal LO, the LO source will be different for both the boards and external calibration is run to provide MCS.

  • Sorry, I don't mean to be nuisance, but I do not quite understand. Can you maybe bare with me and explain a little more?

    So, with AD9361 chips there are two ways of doing RF synchronization as far as I know. First one is using internal LOs of the chips and doing the calibration (using the RF switch to route signals, then calculate the phase differences and then correct the signals using DSP in FPGA).

    The second one is having common external LO for both of the chips and ensuring that there is no clock skew (matched length traces) between the input to both of the chips external LO pins. As the LO used in both chips is common then this should make all RX channels on both of the chips phase-coherent. Is that correct?

    Now I understood from your reply that even when using external LO there is still need for some calibration. What do you mean by calibration and how is this done?

    The reason why I'm asking is because I'm studying the FMCOMMS5 schematics with a purpose of designing my own custom PCB using two AD9361 chips to get 4 phase-coherent RX channels. I would like to achieve this using the external LO option. I think the schematic on FMCOMMS5 is what is needed for this and I would like to take this as a reference, but there is little information about using external LO to achieve RF synchronization.

    Thank you!

  • 0
    •  Analog Employees 
    on Oct 25, 2019 5:26 AM 12 months ago in reply to ronnu

    Even when you are using external LO, there is still an ambiguity due to the dividers, which can cause a phase shift of either 0 degree or 180 degree depending on which phase the divider has come up after power up. So that difference is externally calibrated in baseband or FPGA