Hello,I have 2 questions.
1.In our custom board,we found the data in 2 Rx channel ，phase difference between two channels is 180 degree.
Like this one.
I want to know why the 2 channel phase inversion?
2.If we change the downsampling rate, does the data port clock automatically change? E.g:1) Suppose we want to increase the downsampling rate, reduce the signal bandwidth and data rate;2) Suppose we want to reduce the downsampling rate. For example, the downsampling of several HBs is set to 1, and it works directly at the sampling rate of more than 200 M. Is it ok? Will the data clock at this time naturally increase?
Please see the attribute rx1rx2_phase_inversion_en on the device driver wiki. The phase inversion is inherent to the design. By setting the attribute rx1rx2_phase_inversion_en, the two Rx channels can be phase aligned.
Regardless of the decimation factors chosen, the maximum sample rate from the digital interface to the part is 61.44 MSPS. Similarly, the minimum data rate is 520.833 KSPS.