I'm trying to connect the FMCOMMS5 to a 10MHz rubidium disciplined sine wave reference. R360 and C348 are depopulated and C301 is populated. The device tree includes xo-disable-use-ext-refclk-enable for both chips and the clock frequency is set to 10000000. Both chips fail calibration on initialization and register 0x5e reflects that neither BBPLL is locked. Is there something that I'm missing to this configuration?
Note: The FMCOMMS5 board is running on a ZCU102.
Is the clock input to the ADCLK846BCPZ at U301 also sensitive to low reference clock levels as the AD9361 ext_refclk input is? I measure a 10MHz 1.1Vpp square wave on the AD9361 side of C165. Would you recommend populating C166 to adjust the voltage divider to increase the amplitude of the square wave to 1.3Vpp? Is there a specific capacitance that you recommend?
Moving to the chip-specific forum, since this is more in that area.
Are you able to provide any more support to this issue?
Try using a reference clock of higher frequencies(say 40MHz)and set the divider value to (*2 )and then check if the initialization is completing successfully or not.
Populating the capacitor C166 will not help in increasing the amplitude of your input clock signal, rather it will decrease the level of your input signal. You can try by giving the1.3V p-p input from the external reference directly at the C165 capacitor.
I am taking over this for Griffin since he is off getting his masters degree. I can try to boost the 10MHz voltage level up to exactly 1.3V, but is there any disadvantage to using 10MHz vs. 80MHz? It is difficult to say what is actually going on inside of this chip.