I'm trying to connect the FMCOMMS5 to a 10MHz rubidium disciplined sine wave reference. R360 and C348 are depopulated and C301 is populated. The device tree includes xo-disable-use-ext-refclk-enable for both chips and the clock frequency is set to 10000000. Both chips fail calibration on initialization and register 0x5e reflects that neither BBPLL is locked. Is there something that I'm missing to this configuration?
Note: The FMCOMMS5 board is running on a ZCU102.
Can you provide your device tree (please use Pastebin or something similar)? Can you provide the output of "cat /sys/kernel/debug/clk/clk_summary" too?
Also, what are the specifications of the external reference?
The device tree is at https://gist.github.com/gqk0109/699782fff8a7bd37ebf0cbfda8f81029. The clock summary is at https://gist.github.com/gqk0109/6437ba8155a151cf5cbe5d52d3a04ea7.
The external reference is a 5dBm 10MHz sine wave that is disciplined to a rubidium timebase.
This looks fine. What revision of FMComms5 do you have?
Low reference clock values are known to cause troubles -
Please see here: https://ez.analog.com/wide-band-rf-transceivers/design-support/f/q-a/78979/problem-with-10mhz-external-reference
Is the clock input to the ADCLK846BCPZ at U301 also sensitive to low reference clock levels as the AD9361 ext_refclk input is? I measure a 10MHz 1.1Vpp square wave on the AD9361 side of C165. Would you recommend populating C166 to adjust the voltage divider to increase the amplitude of the square wave to 1.3Vpp? Is there a specific capacitance that you recommend?
Moving to the chip-specific forum, since this is more in that area.