Hi ad9361 experts:
I am using ad9361. I use the FAGC with baseband controls the EN_AGC pin. I use the vivado to observe the control output pins status. Sometime, even the baseband has already pull high the EN_AGC pin, FAGC is still in lock status. Why? The connection between the FPGA and AD9361 is right, because it can unlock in most conditions when the baseband pull the EN_AGC pin high. Can you please give me some suggestion about the situation of ad9361 falis to unlock even the EN_AGC is already high?
Thanks a lot.
Are you using FMCOMMS3 eval board or custom board?
The FAST AGC should always unlock when the EN_AGC pin is pulled high. Is this issue happening all the time? Can you try by giving a high pulse to the EN_AGC pin from an external source instead of giving from FPGA to eliminate connection issues?
Thanks for your reply. I read the related post and found that in this Keeping the AD9361 Fast AGC in locked state (5) post, you mentioned that "The EN_AGC pin should be pulled high for at least 2FB_CLK". If the high level time of unlock signal was shorter than 2 FB_CLK, would this result in unsuccessful unlocking of AD9361 FAGC?
Yes. The EN_AGC pin should be pulled high for a sufficient duration. Also, make sure that the voltage level to the pin is correct which should be VDD_INTERFACE.