Our system uses and AD9361 ("Catalina") chip in N2R2T, DDR, FDD, LVDS mode.
We use an external (FPGA based) Rx to Tx loopback : The received LVDS RX data (with its DATA_CLK and RX_FRAME) is externally looped back towards the LVDS Tx bus (along with the derived FB_CLK and TX_FRAME), with or without intermediate Data processing.
We have met a problem on AD9361's Rx/Tx Delays tuning:
We used a Pseudorandom Binary Sequence Calibration on the LVDS Interface of the AD9361, as per ADI's Application Note "AN-1441" (attached).
We applied both Rx and TX paths testing, exactly as described in the Application note, and managed to get quite good and consistent results on both Rx and Tx Delays.
HOWEVER, when we tried to apply these Rx/Tx delays on our platform on "living" signals (rather than PRBS), we got very poorLVDS bus performance.
In fact, after manually tuning these parameters to get optimal LVDS bus transfers – it seems that the "real life" Rx and Tx Delays are quite different than the PRBS estimated ones !
In our configuration, it may be understood why the PRBS measured Tx Delays (on Catalina's loopback from Tx to Rx bus) are not as in "real life" system ( where the loopback is external, from Rx to Tx bus), since these are 2 different Data paths.
But I would expect the Rx Delays will be the same, since there is no path change between the PRBS Rx Testing and the "real life" mode.
Do you have any explanation for these peculiar phenomena ? (I do believe that some of your customers had already meat such problems…)
Can you suggest another automated/semi-automated method / workaround for Rx/Tx Delays tuning ?
Which software driver are you using? No-Os or Linux?
You can check whether the below is helpful.
Linux. 2015 R2 version.
This process is only valid with your FPGA design
However, we are using a custom board with our FPGA design.
The process described in the link you provided assumes using your supported FPGA host with you VHDL.
However, we are using a custom board with another FPGA. Thus, the process of auto LVDS calibration isn't supported (isn't it?) We're using the driver from R2 2015 which is supported under our kernel.
We need you advice regarding how to find the right values for registers 0x006 and 0x007 (or even more registers involved?).
Procedure is same as explained in the link shared above.
The receive chain is validated first. The AD9361 is programmed to generate a PRBS (PN) BIST pattern at the digital interface. A corresponding (and matched) sequence monitor is implemented in the FPGA. The delay is sweeped from minimum to maximum monitoring the status signals. More precisely the function first sweeps all data delays (0..15) and then all clock delays (0..15). The optimal delay is selected as the mid point of the range where the monitor locks.
Before that you need to ensure that the digital data timing . (Set up and hold) are met as specified in the datasheet.