LVDS Calibration issue in AD9361

Our system uses and AD9361 ("Catalina") chip in N2R2T, DDR, FDD, LVDS mode.

We use an external (FPGA based) Rx to Tx loopback : The received LVDS RX data (with its DATA_CLK and RX_FRAME) is externally looped back towards the LVDS Tx bus (along with the derived FB_CLK and TX_FRAME), with or without intermediate Data processing.


We have met a problem on AD9361's Rx/Tx Delays tuning:

We used a Pseudorandom Binary Sequence Calibration on the LVDS Interface of the AD9361, as per ADI's Application Note "AN-1441" (attached).

We applied both Rx and TX paths testing, exactly as described in the Application note, and managed to get quite good and consistent results on both Rx and Tx Delays.


HOWEVER, when we tried to apply these Rx/Tx delays on our platform on "living" signals (rather than PRBS), we got very poorLVDS bus performance.

In fact, after manually tuning these parameters to get optimal LVDS bus transfers – it seems that the "real life" Rx and Tx Delays are quite different than the PRBS estimated ones !


In our configuration, it may be understood why the PRBS measured Tx Delays (on Catalina's loopback from Tx to Rx bus) are not as in "real life" system ( where the loopback is external, from Rx to Tx bus), since these are 2 different Data paths.

But I would expect the Rx Delays will be the same, since there is no path change between the PRBS Rx Testing and the "real life" mode.


Do you have any explanation for these peculiar phenomena ? (I do believe that some of your customers had already meat such problems…)

Can you suggest another automated/semi-automated method / workaround for Rx/Tx Delays tuning ?