# Maximum Bandwidth and Maximum sample rate

Hi,
I'm using FMCOMMS3 eval board with KC705 FPGA. I want to use whole 56Mhz bandwidth. According to Nyquist theorem, inorder to represent a 56 MHz signal, I need Minimum 112MHSPS(Theoretical) sampling rate. In practical cases it's better to use 2.4*BW(134.4MSPS). But Max sample rate supported by AD9361 is 61.44MSPS. How these numbers will match? Expecting for a positive reply.

Parents
• This topic is an example of extremely discouraging product support from Analog Devices. If you cannot support your customers by using simple and basic terminology, it means that you do not know what you are doing! Instead of giving concise and candid answers, your employees are providing various links to other similar topics, figures even off-zone references. Why not get someone with sharp understanding of underlying concepts and provide solid answers?

Here is the question simplified; Nyquist sampling theorem states that if an analog signal occupies bandwidth of BW ,  in order to represent this signal in digital domain without loss of integrity it should be sampled with sampling rate of 2*BW. Now, according to datasheet of the AD9361, tunable channel bandwidth ranges from 200 kHz to 56 MHz; therefore, if the full bandwidth (56 MHz) is utilized, according to the theorem 2*56=112 MHz sampling frequency is required whereas the chip outputs maximum of 61.44 MSPS. Hence, either there is loss of information or a communication problem between customers and Analog Devices exists. Please cut the role-playing and give us the complete explanation. Furthermore, if you use fancy terms like “complex-bandwidth” please explain what you mean by it while giving concrete examples!

• This topic is an example of extremely discouraging product support from Analog Devices. If you cannot support your customers by using simple and basic terminology, it means that you do not know what you are doing! Instead of giving concise and candid answers, your employees are providing various links to other similar topics, figures even off-zone references. Why not get someone with sharp understanding of underlying concepts and provide solid answers?

Here is the question simplified; Nyquist sampling theorem states that if an analog signal occupies bandwidth of BW ,  in order to represent this signal in digital domain without loss of integrity it should be sampled with sampling rate of 2*BW. Now, according to datasheet of the AD9361, tunable channel bandwidth ranges from 200 kHz to 56 MHz; therefore, if the full bandwidth (56 MHz) is utilized, according to the theorem 2*56=112 MHz sampling frequency is required whereas the chip outputs maximum of 61.44 MSPS. Hence, either there is loss of information or a communication problem between customers and Analog Devices exists. Please cut the role-playing and give us the complete explanation. Furthermore, if you use fancy terms like “complex-bandwidth” please explain what you mean by it while giving concrete examples!

Children
• As per the below post, the ADC sampling rate is 640MHz  which is much above the nyquist criteria.

Please refer to the below digital chain:

The 61.44 MHz is the sample rate at the input of FIR and the RF BW is the bandwidth of the analog filter which is placed at the output of ADC. Now the ADC samples the analog signal at a very high oversampling ratio.So, the ADC clock is much faster than the receive sample rate. Decimating and low pass filtering result in digital samples that represent the analog signal.

-fs/2 to fs/2 is 61.44MHz of bandwidth, and since this is complex you are able to satisfy Nyquist.  The front-end analog filter is limited to 56MHz so that is the maximum usable bandwidth.  Running at these maximum configurations we would be assuming the received signal is oversampled, which is a very very common configuration.

• When you sample a signal with a quadrature IQ ADC, this is done with two ADCs clocked 90 degrees out of phase, this gives you twice the number of bits per second of information effectively doubling the sample rate - a single complex sample is really two samples. For an IQ ADC clocked at 61.44MHz, the digitised bandwith is 61.44MHz (not Fs/2) as you are effectively sampling at 122.8MHz. The bandwidth in this chip is limited by the analogue filter bandwidth of 56MHz so the remaining is oversampling.