We have a AD9361/Zynq-7000 setup, where we are driving the AD9361 with an application based on no-OS (baremetal) that is running on one of the ARM cores of Zynq.
We would like to continuously stream data to dac, preferably using dma, but we are not sure how.
In particular, we are trying to generate our transmit data and transmit it at the same time for a relatively long time. For example, we want to generate 5ms worth of IQ samples and put it in buffer1, dma content of buffer1 to the dac, while this 5ms is being transmitted, we generate the next 5ms worth of IQ data and put it in buffer2, and would like to push buffer2 to dma and dac, and so on. We expect the transmit data to be continuous without any gaps, ie contents of buffer2 is transmitted right after contents of buffer1. We do not know how to do this
Please note that we already are able to, as an example, transmit one piece of data (a single buffer) in cyclic or non-cyclic mode with no-OS, by controlling following registers AXI_DMAC_REG_CTRL, AXI_DMAC_REG_TRANSFER_ID, AXI_DMAC_REG_START_TRANSFER, AXI_DMAC_REG_FLAGS, as well as dac control registers. However, we want to to transmit several buffers by pushing the buffers one after another to dma/dac, and have the dac transmit them continuously.
Thank you for your help in advance.
Can you please check whether the below can help?
Please check the below
Thank you for pointing me to the right direction.
I managed to transmit a stream continuously with two different methods
1) Without interrupt: by monitoring AXI_DMAC_REG_START_TRANSFER, and submitting a new transfer to be queued once the previous transfer queue was successful. Essentially, keeping the dma buffer full at all times.
2) Interrupt based: By modifying the example code for ADC and making the DAC version
I here bring the modifications for future readers
a) dac dma interrupt id
Interrupt ID for DAC DMA is 88Interrupt ID for ADC DMA is 89See FPGA block diagram design, and Zynq-7000 SoC Technical Reference Manual Table 7-4:PS and PL Shared Peripheral InterruptsIn the table, source PL[15:8] is mapped to IRQ ID 91:84. In the FPGA block diagram, DAC_DMA interrupt signal is connected to PL, and ADC_DMA interrupt signal is connected to PL, thus IDs are 88 and 89
b) Make sure the interrupt is routed to the right CPU by calling XScuGic_InterruptMaptoCpu(). In our case, one of the CPUs is running linux, and another is running baremetal, and we did not want the interrupt to be routed to linux cpu