Hi ad9361 experts:
In the default_init_param, there are many parameters to initialize ad9361. I want to know how to optimize these parameters, especially for some threshold value in the agc control, like gc_lmt_overload_high_thresh, which is 800 default. How this 800 come? And how should I optimize this parameter and other threshold parameters to satisfy different situation?
Thanks a lot
LMT overload thresholds and ADC overload thresholds need to be coupled together. That is, if LMT peak detector indicates overrange for a certain sample, then ADC peak detector also needs to indicate the same, unless the LMT overrange is caused by an out-of-band interference signal. Additionally, ensure that only a few large ADC overloads occur i.e., the number of +/-4 values at the output of ADC are few, which indicates that the ADC is more or less able to track the input signal. See the register map manual regarding registers 0x2B8 and 0x2B9 and the bits to read to detect LMT and ADC overloads.
AGC lock level indicates the expected average power of the waveform to which we want to match the measured average power at the output of halfband decimators by tuning the AGC. So, this setting is highly waveform specific. Collecting statistics offline using your waveform to determine its average power is probably the way to go for this step.
A couple of other parameters such as AGCLL Max Increase, LMT/ADC large/small decrements depend on how much variation exists in the received waveform and how quickly you want the AGC to lock to the optimal level. If the waveform has large variations i.e., the AGC might need to traverse from gain index #76 to #1 (and vice-versa) within a short period of time and you want the AGC to lock quickly, then the increment/decrement step sizes need to be large so that large gain changes made in relatively short time. These settings are again highly waveform/channel environment dependent.
Thanks a lot.
I read AD9361 Gain Control and RSSI User Guide_v2.9, it says when Large ADC V Large LMT V Digital Sat happens in State 1 of FAGC, the gain step size is set by 0x106[D6:D4], but I can not find parameter in no-os to set this register. Could ou please give me some advice?
Besides, what is the step size when changing the gain to match the lock level in state 2 of FAGC?
We want to lock the gain in 4us, and I tried to change different parameters of FAGC to optimize the lock time, but still the gain can not lock during 4us, any suggestion please?
All the device parameters including those related to gain step size are accessible through the default_init_param structure in main.c.
>> what is the step size when changing the gain to match the lock level in state 2 of FAGC?
The step size is calculated within the part based on the difference between lock level and current measured average power. It is not a parameter set by the user.