ad9361_dig_tune_delay: Tuning RX FAILED!

i designed a custom ad9364 eval board.i used  hdl-hdl_2018_r1 & no-OS-2018_R1 for no-os on my zedboard

 i changed to AD9364 in config.h  no-OS project 

#define AD9361_DEVICE 0         /* set it 1 if AD9361 device is used, 0 otherwise */
#define AD9364_DEVICE 1        /* set it 1 if AD9364 device is used, 0 otherwise */
#define AD9363A_DEVICE 0    /* set it 1 if AD9363A device is used, 0 otherwise */

when i debug the project .this error shown in serial-terminal


SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_dig_tune_delay: Tuning RX FAILED!
ad9361_init : AD936x initialization error
Failed to restore state
Failed to restore state

I searched for a solution to this problem.and I found different answers

Somewhere it is said that the problem is from the input clock but my input clock source is ocxo with level 1.3v and 40MHZ frequency

Another solution that was presented is that change the value "digital_interface_tune_skip_mode" to 2 in main.c AD9361_InitParam default_init_param = {

I did it and changed to 2.The problem was resolved and no errors are displayed.

Is this really the right thing to do ? Does system performance decreasing?

i connected TX1 & RX1 together. the ADC IQ output is 

 

when i changed rx1_gc_mode from 2 to 0 (rx1_gc_mode=0) .The IQ is as follows

and finally i changed dds_tx1_tune1_freq=5000000 & dds_tx1_tune2_freq=5000000  & The IQ is as follows

 i plot IQ data(iladata.csv) in matlab 

why in iladata.csv  each sample is repeated twice?

Is the AD9364 function correct ????



Added samples
[edited by: osamu.fu64@gmail.com at 11:53 AM (GMT -5) on 4 Nov 2018]
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