AD9361: tx filter configuration

Hello!
I see strange strings in function "ad9361_load_fir_filter_coef" of file "ad9361.c":
...
"
for (val = 0; val < ntaps; val++) {
ad9361_spi_write(spi, REG_TX_FILTER_COEF_ADDR + offs, val);
ad9361_spi_write(spi, REG_TX_FILTER_COEF_WRITE_DATA_1 + offs,
coef[val] & 0xFF);
ad9361_spi_write(spi, REG_TX_FILTER_COEF_WRITE_DATA_2 + offs,
coef[val] >> 8);
ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs,
fir_conf | FIR_WRITE);
ad9361_spi_write(spi, REG_TX_FILTER_COEF_READ_DATA_2 + offs, 0); /// ???
ad9361_spi_write(spi, REG_TX_FILTER_COEF_READ_DATA_2 + offs, 0); /// ???
}
"
where
REG_TX_FILTER_COEF_READ_DATA_2 = 0x064 (R)
REG_TX_FILTER_COEF_READ_DATA_2 = 0x064 (R)
Look at datasheet "AD9361 Register Map", section "TRANSMITTER CONFIGURATION", table "TX PROGRAMMABLE FIR FILTER REGISTERS 060 THROUGH 065". Register "TX Filter Coefficient Read Data 2" is read only (R). Why I must write to address REG_TX_FILTER_COEF_READ_DATA_2 some value? What is the purpose of writing?

Who can help?

Thanks in advance!

Evgeniy

    •  Analog Employees 
    on Mar 5, 2018 10:13 AM over 2 years ago

    There is a limitation on how fast the FIR coefficients can be written into the AD9361. The coefficients are latched into the registers using the FIR output clock. To ensure each coefficient is written correctly into the desired register, the user must allow two FIR output clock cycles to elapse before updating the coefficient address or data. If the SPI clock is too fast relative to this delay, the user could write a new address or data value prior to the coefficients being properly latched by the FIR output clock. The user may have to include WAIT or NOP statements to allow two FIR output clocks to transpire while address and data are stable. This is illustrated in the driver by using two consecutive writes to read-only registers.

    -Michael