- What information should I provide to help speed resolution of my issue?
Please provide as much detail as possible including all of the detail described in the table below
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Detail |
Comments |
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Issue Summary |
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Issue Details |
Provide any associated plots, screen captures, etc that will help ADI to understand the issue |
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Workaround (if applicable) |
Describe any workaround you have found |
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Sequence to reproduce issue |
Describe sequence that causes issue to occur |
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Repeatability |
Does the issue occur all of the time or occasionally. If occasionally describe how often |
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No. parts affected |
Does the issue occur on all parts or a sub-set of parts. If a sub-set, how many and what percentage? |
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Use Case Details |
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RF LO Frequency, Use Case No. TDD/FDD timing details |
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Software Version(s) |
Detail software versions (API, Firmware and Stream versions) that show the issue |
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API Log |
Attach API log if applicable |
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- What are the key specifications of ADRV9026 chip?
- The ADRV9026 is a 4 Transmit/ 4 Receive/ 2 Observation Receive transceiver chip supporting both TDD and FDD operation.
- Local Oscillator frequency range supported currently is 650 MHz to 6 GHz (will be extended to 75 MHz to 6 GHz in 2020).
- Channel Bandwidth: 200MHz Rx, 200MHz Tx large signal, 450MHz Tx Synthesis, 450MHz ORx.
- Max Serdes rate: 16Gsps (operation to 25Gsps is currently sampling with release planned in 2020.)
- Max Tx Output power is +7dBm with a CW signal
- Does the ADRV9026 chip support both TDD and FDD operation? How many RF LO’s are there?
- Yes ADRV9026 supports both FDD and TDD operation.
- There are two RF LO’s that provide flexible connection options for the Tx and Rx channels. Hence chip can support configurations like
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- TDD 4T4R single band
- FDD 4T4R single band
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.
- Where can I find user guide and schematics for ADRV9026?
- User Guide, schematics and other documentation are included in the Design File Package, available on the ADRV9026 landing page.
- Where can I find the evaluation software for ADRV9026?
- The Software Package includes the evaluation GUI software, the API source code, the firmware, and the gain tables, available on the ADRV9026 landing page.
- What are the evaluation kits for ADRV9026?
- There are two options of evaluation kits: ADRV9026-HB/PCBZ for high-band matching 2.8GHz to 6GHz and ADRV9026-MB/PCBZ for mid-band matching 650MHz to 2.8GHz. Both work with the ADS9-V2EBZ as motherboard. Please visit the ADRV9026 EVB page for more information.
- Does ADRV9026 support MC-GSM?
- No, The device supports small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations
- Does ADRV9026 support internal DPD?
- ADRV9026 does not have internal DPD. It supports observation receive with 450 MHz bandwidth for implementing external DPD. A Future version will support internal DPD.
- Can ADRV9026 support fast frequency hopping?
- The current ADRV9026 has not been optimized for frequency hopping but this feature will be added in the future software upgrades.
- Can ADRV9026 support external LO?
- The current ADRV9026 doesn’t support external LO but this feature will be added in the future software upgrades.
- Will ADRV9026 support 5G operation?
- Yes, the ADRV9026 has RF performance specifications to enable 5G applications and supports TX and RX minimum on times down to 100us to enable 5G TDD operation.
- What is the typical power consumption of ADRV9026 in TDD and FDD mode?
- The power consumption depends on the programmed configuration. Typical power consumptions are~5W for TDD mode and ~7W for FDD operation for 200MHz primary BW.
- ADRV9026 supports both JESD204B and JESD204C, Will there be a difference in clocking (Device clock and SysRef) for JESD204C? Can AD9528 support both JESD204B and JESD204C?
- The device clock and SYSREF are both required for JESD204B and JESD204C operation – there is no difference in the physical clocking requirement for the two modes. The AD9528 clocking device on the EVB can support both JESD204B and JESD204C operation.
- How much is the typical boot-up time and initial calibration time for ADRV9026?
- Typical boot-up time for the part is ~4sec, dependent on SPI clock rate. The time required for initialization calibrations varies depending on the use case. In JESD204B use cases, it is ~4sec per enabled channel, so for 4 channels, it takes about 16 sec.
- The ADI evaluation platform currently has a longer boot up time which is unrelated to the ADRV9026 boot time. It takes approximately 3 minutes for bootup. Check for Red LED on the MicroZed going off which indicates boot up is complete.
- Can customers create custom profile? Is there a configuration wizard available?
- Currently customers must use the provided profiles – a configuration wizard will become available in a later release. Please note only the use cases included in the Windows GUI are currently supported until the filter configuration wizard is available later 2020.
- Does ADRV9026 support RF PLL phase sync? What is the phase accuracy of TX ports?
- RF PLL phase sync is supported on the ADRV9026.
- The initial phase sync accuracy is 0.9ps.
- Will ADI provide reference software in Wiki page (linux and No-OS) like for other transceivers?
- Currently the prototyping software (Linux & No-OS) is not available on wiki.
- For TDD operation what is the minimum ON period required for Tx and Rx for tracking calibrations?
- Minimum ON time for both TX and RX tracking calibrations to progress is 100us.
- What is the resolution of ADC and DAC used in Tx/Rx and Orx path? What is the dynamic range of Rx chain? What’s the max sampling rate of ADC and DAC?
- Tx path DAC is 14 bits, Rx/Orx path ADCs are 16 bits. Rx SFDR is 81dBc.
- DAC max rate 2.5Gbps and ADC max rate 5Gbps.
- Where can I find S-parameter files and JESD simulation files?
- S-parameters and JCOM model for JESD simulations are part of the design file package available on the ADRV9026 landing page.
- JCOM: Requires customers to have Matlab plus RF toolbox JCOM reads touchstone files and uses a few Matlab functions, but it could be moved to other ecosystem (such as python).
- How much insertion loss is supported for 25G Serdes link?
- ADI is currently validating insertion loss ranges from 8-15dB. Future releases are expected to expand this range from 2 to 20dB. For insertion loss ranges beyond 8-15dB please contact ADI for specific recommendations.
- What gain control modes are supported on Rx?
- ADRV9026 supports both manual gain control (MGC) and automatic gain control (AGC) modes
- Does ADRV9026 support AGC operation where gain update counter is larger than the Rx time slot in TDD?
- Yes ADRV9026 does support this AGC mode
- Does ADRV9026 support sharing framer for both Rx and ORx channels?
- Yes ADRV9026 supports link sharing mode, where both the Rx and ORx used the same JESD framer link. This mode is useful for TDD applications.
- Does ADRV9026 support ADC crossbar control using ORx_EN pin in link sharing mode?
- Yes, the user can enable the feature where they can set the ADC crossbar to ORx channel when ORx_EN goes high and restore the cross bar to Rx channel when ORx_EN goes low.
- What’s the package of ADRV9026?
- 14 mm x 14 mm 289-ball BGA
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