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how to set the value of cfrtxdelay in cfr of adrv9025

Category: Hardware
Product Number: adrv9025
Software Version: sw6.3.0.5

Hi Ramarao and any other experts :

the value of cfrtxdelay in the api adi_adrv9025_cfrcontrolconfig set  is limied to 129~511,

Is this mean we can select any value between 129 and 511?

Is the value of cfrtxdelay in each cfr engine related with the lenght of correct pulse?

How to select the optimal value of cfrtxdelay for specific usecase? 

Is there any guide for select the value of cfrtxdelay?

Thank you very much!

  • The CFR Delay RAM FIFO is used to delay the input signal so that there is enough time to detect, process, and correct peaks within the input signal.

    The required latency per engine is roughly equal to "1.5 * half_pulse_length / interpolation". Adding extra latency is acceptable, but generally not preferred due to low latency requirements on the full system.

    Is this mean we can select any value between 129 and 511?

    Yes, you can select the delay. Please check the CFR performance versus delay of your system requirement. The more the delay, the more the probability of detecting the peaks and so the cancellation, however it would impact your system delays.

  • Hi  Ramarao,

                      Thank you for your  explain about cfrtxdelay.

                       More questions about CFR in adrv902x.

                      1.Can we use  our own correction pulse coeff  to replace the ones adi provided with  matlab files?

                        we will follow the fromat of  pulse coeff  generated by .m files.

                       2.The latency for CFR in the userguide  is calculated as follow formula:

                          (cfrtxdelay + 1) * enabled engine + 3 (hardclipper latency)

                          This expression is different with roughly equal to "1.5 * half_pulse_length / interpolation"

                           Is there  any error in the  formula?

                         3. In my opinion, the pipeline delay is related to both cfrtxdelay and no of  eanbled engine. Howerver  he pipeline delay read back from adrv902x in our board seems to be just related with cfrtxdelay,having no  concern with no of cfr engine enabled, Is this right?  Why?

                         Thank you!

  • We are working on this, will get back ASAP

  • Q1:This is fine, no issue as long as the CFR pulse format is same as what we have.

    Q2: The vlaue, "cfrTXdelay+1" is roughly equal to "1.5 * half_pulse_length / interpolation"

    With a half pulse length of 512, and with interpolation of 1 to 4, the delay can be 192 to 768 but we limit the cfrTxdelay parameter to 511 in our configuration.

    Q3: The cfrTxdelay parameter readback is per engine.

  • Hi Ramaro,

                    Q3: I mean using the API cfrpipelinedelayget to read back delay time.

                           For example,  set the cfrtxdelay to 511 , 3 stage cfrs and hard clipper enabled ,then  retrieve value is 1536.

                            If  the  return value from API "adi_adrv9025_CfrPipelinedelayGet()" refers to total delay  through the cfr block?

                            Thank you very much!



  • We will get back on this at the earliest possible.