ADRV9025 PLL Unlock

The limitation could be coming from the integer / fractional synthesizer mode of the PLL. What is the reference clock in your setup? Refer page 75 of the UG for more details.

Can you change the PLL1 frequency to 3761 or 3760 and see if the LO is getting locked? 

Hi

Could I set each  channel for different frequency  look like Tx1 to 900Mhz

                                                                                             Tx2 to 1800Mhz

                                                                                            Tx3  to 12500Mhz

 and                                                                                     Tx  to 3.5 Ghz

Many thanks

Rich

No, that's not possible as the chip does have only 2 LOs.

Hi 

Any possibility to use external LO?

Best Regards

Rich

No, the chip does not support External LO

Many Thanks

Many Thanks