We have 16 ADRV9026 mounted on a single board, everyone is clocked by the same signal and multi-chip sync procedure is successfully performed.
All chips, and all chip channels are fed by a CW signal @3 GHz with power tuned to have around 0dBFS on digital part.
RX samples are simultaneously dumped by our FPGA through JESD connection.
What I see is different phases on each chip, and this is normal as electric paths are slightly different on board itself,
but every time I perform the procedure described in user manual, "CALIBRATION GUIDELINES AFTER PLL FREQUENCY CHANGES",
phase differences between chips varies (up to +-15 deg), even if we don't modify RX pll frequency.
How can it be ?