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ADRV strange PHASE behaviour after calibration procedure

Hello,

We have 16 ADRV9026 mounted on a single board, everyone is clocked by the same signal and multi-chip sync procedure is successfully performed.
All chips, and all chip channels are fed by a CW signal @3 GHz with power tuned to have around 0dBFS on digital part.
RX samples are simultaneously dumped by our FPGA through JESD connection.

What I see is different phases on each chip, and this is normal as electric paths are slightly different on board itself,
but every time I perform the procedure described in user manual, "CALIBRATION GUIDELINES AFTER PLL FREQUENCY CHANGES",
phase differences between chips varies (up to +-15 deg), even if we don't modify RX pll frequency.

How can it be ?

BR

Pietro

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  • All chips, and all chip channels are fed by a CW signal @3 GHz with power tuned to have around 0dBFS on digital part.
    RX samples are simultaneously dumped by our FPGA through JESD connection.

    Can you test with -5dBFS signal level?

    What I see is different phases on each chip, and this is normal as electric paths are slightly different on board itself,
    but every time I perform the procedure described in user manual, "CALIBRATION GUIDELINES AFTER PLL FREQUENCY CHANGES",
    phase differences between chips varies (up to +-15 deg), even if we don't modify RX pll frequency.

    Are you seeing a different phase at the same frequency from run to run? Hope you are calibrating only when there is a frequency change. Is your frequency change falliing in Type 1 or Type 2. For Type 2, you will have to run ADI_ADRV9025_LOOPBACK_RX_LO_DELAY and
    ADI_ADRV9025_TX_QEC_INIT calibrations additionally on top of Type 1 cals.

Reply
  • All chips, and all chip channels are fed by a CW signal @3 GHz with power tuned to have around 0dBFS on digital part.
    RX samples are simultaneously dumped by our FPGA through JESD connection.

    Can you test with -5dBFS signal level?

    What I see is different phases on each chip, and this is normal as electric paths are slightly different on board itself,
    but every time I perform the procedure described in user manual, "CALIBRATION GUIDELINES AFTER PLL FREQUENCY CHANGES",
    phase differences between chips varies (up to +-15 deg), even if we don't modify RX pll frequency.

    Are you seeing a different phase at the same frequency from run to run? Hope you are calibrating only when there is a frequency change. Is your frequency change falliing in Type 1 or Type 2. For Type 2, you will have to run ADI_ADRV9025_LOOPBACK_RX_LO_DELAY and
    ADI_ADRV9025_TX_QEC_INIT calibrations additionally on top of Type 1 cals.

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