we have developed a board which uses five ADRV9026 chips to implement 20 TX and 20 RX channels. After the initialization process, according to the UG-1727 System Development User Guide. However, we have different phase relationships every time we power up the board and different chips seems random.The same chip is stable.
The JESD204B interface works fine and the statuses seem to be OK.
We had set the rfPllPhaseSyncMode to 2. Our SYSREF frequency 3.84MHz.
What could be the reason for this problem? And how to Dthis problem.
We have try some test and result below.
1.I had try to set my LO frequency to 1531.5MHz，when every time we power up the board phase seems random.
2.But when we set my LO frequency relate to my SYSREF,such as 1536MHz（3.84*400=1536）,it works. when every time we power up the board phase,it stable.
I want to know how difference LO frequency may lead to difference result. And when I use1531.5MHz LO how to let all chips phase stable when every power-up.