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AD9528 input reference clock changing to RefB.

Hi,

We were configuring the AD9528 with input Ref clock REFA  and VCXO .The configuration was successful. Now we want to change the input Ref clock to REFB instead of REFA, for this I have changed registers

0x0108 from value 0x2a to 0x52

0x010a from value 0x2 to 0x3

With the above changes after configuring the AD9528 when I am reading the readback register 0x0508 the value is found to be 0xea . This means the PLL1 is not getting locked.

While change the input reference clock from REFA to REFB is there any other register we need to change apart from the above mentioned registers ?

Thank You in advanced .

  • It looks like you are operating in the manual switchover of the reference.

    What is the Ref B frequency and the level of the signal?

    If possible, can you try feeding the Ref A input at Ref B and see if the PLL1 is getting locked?

    There are no other registers to be configured.

  • Hi Ramarao,

    Thanks for your response.

    It looks like you are operating in the manual switchover of the reference.

    Yes you are right.

    What is the Ref B frequency and the level of the signal?

    The REFB frequency is 122.88MHz and the signal level is 700mV.

    If possible, can you try feeding the Ref A input at Ref B and see if the PLL1 is getting locked?

    We have tried this exercise and both the PLLs are getting locked but the ADRV9029 initialization is getting failed.

    AD9528 is not getting configured properly, as the expected output clock are not seen (devclks and sysrefs).

    How to change the REF clock for AD9528  to REFB in the ADRV9029 driver source code ? 

    Please let us know what are the other changes has to be done in the ADRV9029 driver source code apart from the registers change mentioned above for AD9528 . 

  • We will check this and get back to you

  • You may need to modify the Ref. B divider as shown below:

    Can you check and confirm? Further, pls check the below post for additional help.

    ez.analog.com/.../305954

  •  Hi Ramarao,

    I have gone through the link that you have provided and we are modifying the registers of AD9528 in  devices/ad9528/public/src/adi_ad9528.c as well.

    As mentioned we have modified the register 0x0102 (PLL1 Ref B divider) to value 0x02 according to the input reference clock for REFB that is 122.88MHz (by taking the register dump from AD9528 GUI). After the modification, for input reference clk 122.88Mhz when we directly feeding it to REFB and the PLLs are getting locked as I can see the read back status register value as 0xEB. Now on the  output,  the device clocks are there for ADRV9029 and FPGA but the sysrefs are missing .

    Thanks

  • Are you configuring syref generation in continuous mode or single pulse mode?.

    Can you please try the below API to trigger the sysref pulse and see whether you are able to see the sysref output from AD9528?

    /**
    * \brief Send a SPI message to request a SYSREF pulse or continuous SYSREF from
    * the AD9528
    *
    * Requests a SYSREF from the AD9528. It will use whatever settings for SYSREF
    * that are current configured in the AD9528. This could be a single pulse,
    * multiple pulses, or continuous pulses.
    *
    * <B>Dependencies</B>
    * - device->common.devHalInfo
    *
    * \param device is structure pointer to AD9528 clock device structure
    * \param enableSYSREF If NSHOT SYSREF mode, this parameter is ignored. If
    * PRBS/CONTINUOUS SYSREF mode, 1= enable SYSREF, 0= disable SYSREF.
    *
    * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action
    * required
    */
    int32_t adi_ad9528_SysrefRequest(adi_ad9528_Device_t *device, uint8_t enableSYSREF);

  • Hi ,

    The clock issue is resolved. In the ADRV9029 driver source code in function adi_ad9528_PllLockDebounce the PLL lockflag was always 0 since it was set according to Ref A. Changing it for Ref B fixed the issue.

    Thank You !