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ADRV9026 adi_adrv9025_CpuStartStatusCheck show "ldo configuaration error"

my adrv9026 cpu start check  report  error "CpuBootStatus_e: 16 - LDO Configured Incorrectly "

i use "nobypass ldo"  configure  in my setting

the error status is:

when issure  "adi_adrv9025_CpuStart" function,

VRFVCO1_1P0 :     700mv--->0V(380ms)-->700mV

VRFVCO2_1P0 :     700mv--->0V(380ms)-->700mV

VAUXVCO_1P0:   700mv--->0V(380ms)-->700mV  

do not achive to 1.0V level.

my adrv9026 chip production batch is: 1942(2019,42week)。 the function “ldo nobypass“ is useful?

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  • added: vclkvco_1p0 when ldo_enable function is over . the volatge is 200mv about.  and when cpu start is over,  the volatge changed from200mv to 950mv.   

  • ADRV9025/6  uses internal LDO's and ldoSelect  should be 0.

    I guess you are working on custom board. You can use external power supply for the 1.3V supply if you suspect that the power supply is unable to provide the required currents.

  • n my design,  Tx1 to Tx4 no need and i unconnected these pins.   It is incorrectly ?

    Yes. Are you disabling these unused channels in software as well. ? 

  • When issue is seen can you read back below registers.

    SPI Read Address 0x11c: 0x14L
    SPI Read Address 0x111: 0x8L
    SPI Read Address 0x112: 0x28L

    Also share full log files during boot up.

    Also run SPI verify API and share. adi_adrv9025_SpiVerify() 

    It is recommended prior to configuration to toggle the RESET signal after power has stabilized. The RESETB signal needs to be pulled down for 1ms , and then pulled up. Wait for 100us and then start to initialize the chip. RestB Should be high for normal working mode.

  •          It is my io set in my design.   I think it is strictly follow the reference of ug-1727.  Only some pins are directly to fpga ios (rxn_p/n), no have pull down resistance to VSSA.  I use io pull down to 0 when the app start work.

            Added:  The power tree layout of my design is not strictly follow UG-1727.  The main diference is the pcb layout not the star connection but the electric current is enough.

  • Has this been checked?

    When issue is seen can you read back below registers.

    SPI Read Address 0x11c: 0x14L
    SPI Read Address 0x111: 0x8L
    SPI Read Address 0x112: 0x28L

    Also share full log files during boot up.

    Also run SPI verify API and share. adi_adrv9025_SpiVerify() 

    It is recommended prior to configuration to toggle the RESET signal after power has stabilized. The RESETB signal needs to be pulled down for 1ms , and then pulled up. Wait for 100us and then start to initialize the chip. RestB Should be high for normal working mode.

    Can you please share us the Power supply input part of the schematic?

    Are the Supplies within the tolerance?

    Are you following the Power supply sequence as explained in the UG?

  • I will issure these tomorrow because the target board is not beside me.  Power supply sequence are referenced ug1727.  VDIG_1P0 first power up and 25ms later anothers up.

  •              I have verifyed these recommendations and no changes. 

                 After reset toggled, adi_adrv9025_SpiVerify() will first enabled and no problem. RESETB  lower level wait 2ms , and change to level 1 and wait 2ms.  

                   befor enable ldoEnable()          after enable  ldoEnable()        after enable cpu_start()

    0x11c::       0x1CL                                             0x0CL                                          0x0CL

    0x111:        0x08L                                              0x08L                                           0x08L 

    0x112:        0x28L                                              0x28L                                           0x08L 

  • Which precondition should careful about VCLKVCO_1P0,  VAUXVCO_1P0 ?    Is ad9528 outclks has some realation with this this apperance?

  • Can you please provide the supplies, 1.8V, 1.3V and 1.0V individually instead of 12V and check?

  • ADP1763 is a Offical used ldo.  I want know the actual power accuracy ripple range.  What is the judgment basis of these channel‘s voltage?

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