ADRV9026 adi_adrv9025_CpuStartStatusCheck show "ldo configuaration error"

my adrv9026 cpu start check  report  error "CpuBootStatus_e: 16 - LDO Configured Incorrectly "

i use "nobypass ldo"  configure  in my setting

the error status is:

when issure  "adi_adrv9025_CpuStart" function,

VRFVCO1_1P0 :     700mv--->0V(380ms)-->700mV

VRFVCO2_1P0 :     700mv--->0V(380ms)-->700mV

VAUXVCO_1P0:   700mv--->0V(380ms)-->700mV  

do not achive to 1.0V level.

my adrv9026 chip production batch is: 1942(2019,42week)。 the function “ldo nobypass“ is useful?

Top Replies

    •  Analog Employees 
    Sep 15, 2021 in reply to baisuansuan +1 verified
    First, my chip silicon version(register 0x5) in my board is 0xA3, and it's Product Data is 1942(2019, 42weeks). It is an early silicon chip.  But I could only download software SW5…
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  • added: vclkvco_1p0 when ldo_enable function is over . the volatge is 200mv about.  and when cpu start is over,  the volatge changed from200mv to 950mv.   

  • 0
    •  Analog Employees 
    on Sep 14, 2021 4:08 AM in reply to baisuansuan

    ADRV9025/6  uses internal LDO's and ldoSelect  should be 0.

    I guess you are working on custom board. You can use external power supply for the 1.3V supply if you suspect that the power supply is unable to provide the required currents.

  • I read my chip silicon version(register address 0x5)is 0xA3(however Offical Board is 0xB0) 。my software version is SW5.1.0.27.  ADI Product Change Notice(PCN) Report means Software release version 5.0.1 or a later version must be usedwith B0 silicon(publication Data is 30-Nov-2020).  I need a matched software version for this current debug period.   my

  • 0
    •  Analog Employees 
    on Sep 14, 2021 9:49 AM in reply to baisuansuan
    Software release version 5.0.1 or a later version must be usedwith B0 silicon

    5.1.0.27 is a later version and it will work with B0 silicon. Make sure that you use Arm binary files from this package and also install the GUI from SW package 5.1.0.27 and generate init data.c and stream files from that package.

  • yes,I'm sure all software version is correctly(contains gui; library; package; init_data.c). because I have completed debug in a hardware platform which is togethered with an offical adrv9026 daughter board and a specific motherboard (my own, fpga is zynq7100 ) .  the current error occurs when all hardwre designed is newest.

  • 0
    •  Analog Employees 
    on Sep 15, 2021 8:50 AM in reply to baisuansuan

    Can you please follow the below post which has reference to your issue? This could be something to do with 1.3V supply.

    https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9026/f/q-a/534585/adrv9026-ldo/386794#386794

  •     First, my chip silicon version(register 0x5) in my board is 0xA3, and it's Product Data is 1942(2019, 42weeks). It is an early silicon chip.  But I could only download software SW5.1.0.27 from offical website for match.   the offical PCN report said this softtware version must match silicon version is 0xB0.  I Guess this Mismatching is main problem.     

         Added:  My Problem maybe not same with you ,  because I find some special features: when  I issure adrv9025_MasterBiasSet(), VCLKVCO_1P0  achieve to about  80mV but not 0V, and then when enable adrv9025_LdoEnable() function,my  VCLKVCO_1P0  vlotage achieve to about 200mV.   

    when enable adi_adrv9025_CpuStart().   VCLKVCO_1P0 from 200mV achieve to 956mV about(Oscilloscope display 950mV~960mV about).  About 380ms later, when VRFVCO1_1P0、VRFVCO2_1P0 and VAUXVCO_1P0 boost form 0V,this channel output(VCLKVCO_1P0)are Very stable in 950mv, no have any ripple in my oscilloscope. I use same environment check VCONV1_1P0、VCONV2_1P0 and Offical Evaluation Board's VCLKVCO_1P0,Oscilloscope display is a same value about 986mV.   So I Guess my chip inside have some wrong with soft Trim function in  the channel  of VCLKVCO_1P0.

  • +1
    •  Analog Employees 
    on Sep 15, 2021 11:16 AM in reply to baisuansuan
    First, my chip silicon version(register 0x5) in my board is 0xA3, and it's Product Data is 1942(2019, 42weeks). It is an early silicon chip.  But I could only download software SW5.1.0.27 from offical website for match.   the offical PCN report said this softtware version must match silicon version is 0xB0.  I Guess this Mismatching is main problem.     

    The Silicon rev. A3 works with the latest GUI SW as well and so mismatch is not the problem. The PCN document states that Silicon Rev. B0 needs to have GUI SW version higher than 5.0.0.68.

    As the combination, your own fpga is zynq7100 + ADRV9025 daughter card works fine and only the custom board has this issue, please check if the supplies are able to drive enough currents and check 1.3V supply rail.

  • When faced this problem, I first doubt the 1.3V analog rail.  I recheck all pins which 1.3V power supply(I use oscilloscope probe placed to a bypass capacity which is directly under the pin i want measured).  

    the ground point i select a point nearby(about 2mm copper and 30mm cable to the  pen).   I Set a trrigle 1.284V and my oscilloscope have any result. Then I enable such functions,and no any triggle result for these operations.  Is some new information i need focus in ?   

            my power tree have some difference with offical board:

    i use a LTM4644 to change 12V to 1.5V volatge, and then I use a LDO(ADP1763) to 1.3V rail.  VANA1_1P3,VANA2_1P3,VCONV1_1P3, VCONV2_1P3, VCLKVCO_1P3, VRFVCO1_1P3, VRFVCO2_1P3, VAUXVCO_1P3  these channel I use bead to 1.3V analog。 other 6 channels  supplied directly from the 1.3V analog。 this placement is referenced with UG1727 page 226.

            another difference:  my power  sequence is  VDIG_1P0 first use 25ms form 0V achieve to 1.0V and about 25ms later other power rails is ok.

Reply
  • When faced this problem, I first doubt the 1.3V analog rail.  I recheck all pins which 1.3V power supply(I use oscilloscope probe placed to a bypass capacity which is directly under the pin i want measured).  

    the ground point i select a point nearby(about 2mm copper and 30mm cable to the  pen).   I Set a trrigle 1.284V and my oscilloscope have any result. Then I enable such functions,and no any triggle result for these operations.  Is some new information i need focus in ?   

            my power tree have some difference with offical board:

    i use a LTM4644 to change 12V to 1.5V volatge, and then I use a LDO(ADP1763) to 1.3V rail.  VANA1_1P3,VANA2_1P3,VCONV1_1P3, VCONV2_1P3, VCLKVCO_1P3, VRFVCO1_1P3, VRFVCO2_1P3, VAUXVCO_1P3  these channel I use bead to 1.3V analog。 other 6 channels  supplied directly from the 1.3V analog。 this placement is referenced with UG1727 page 226.

            another difference:  my power  sequence is  VDIG_1P0 first use 25ms form 0V achieve to 1.0V and about 25ms later other power rails is ok.

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