ADRV9026 multi-chip phase synchronization

We have developed a board which uses two ADRV9026 chips to implement 8 TX and 8 RX channels. After the initialization process, we expected to have a fixed, consistent phase relationship between the two ADRV9026 chips, since according to the UG-1727 System Development User Guide, the LO PLLs are phase-aligned at the MCS stage of the initialization. However, we have different phase relationships every time we power up the board. The JESD204B interface works fine and the statuses seem to be OK. What could be the reason for this problem?



corrected typos
[edited by: haimf at 12:31 PM (GMT -4) on 20 Jul 2021]
  • 0
    •  Analog Employees 
    on Jul 20, 2021 12:31 PM

    Please make sure you are enabling the " Enable RFPLL phase sync init and track continuously" in the init data.c.

      

  • Thanks for your prompt reply. You were correct, phase sync init & tracking was not enabled. We enabled it, but unfortunately it is still not working. Is there a way of checking the MCS status to see if the PLL phase sync function was executed properly?

    Thanks!

  • 0
    •  Analog Employees 
    on Jul 21, 2021 11:27 AM in reply to haimf

    We can only enable/ disable Phase sync and we don't have any function/ API to check the MCS status.

    Could you please share us the detailed logs? 

  • [01] [00011] TRACE | initHWPreMCS> Start PreMCS_Init MAD 1
    [00] [00011] INFO  | setLogLevel> Module [PLATFORM] log level [2]
    [01] [00011] FATAL | adi_board_adrv9025_Program_Phase1> = Start =
    [01] [00012] WARN  | adi_adrv9025_HwReset>  = Start A. HW reset =
    [01] [00013] WARN  | adi_adrv9025_HwReset>  = End A. HW reset =
    [01] [00013] WARN  | adi_adrv9025_SpiCfgSet>  = End A.2. Spi config =
    [01] [00013] WARN  | adi_adrv9025_SpiCfgSet>  = Start A.2. Spi verify =
    [01] [00014] WARN  | adi_adrv9025_SpiCfgSet>  = End A.2. Spi verify =
    [01] [00015] WARN  | adi_adrv9025_PreMcsInit_v2>  = Start Pre Mcs Init =
    [01] [00015] WARN  | adrv9025_MasterBiasSet>  = Start B.set master bias =
    [01] [00217] WARN  | adrv9025_PadConfigsSet> = Start C.Enable pin pads =
    [01] [00218] WARN  | adrv9025_PadConfigsSet> = End C.Enable pin pads res[0] =
    [01] [00218] WARN  | adi_adrv9025_ProfilesVerify> = Start =
    [01] [00218] TRACE | adrv9025_ProfilesVerify> = Start =
    [01] [00219] TRACE | adrv9025_ProfilesVerify> = End res [0] =
    [01] [00219] WARN  | adi_adrv9025_ProfilesVerify> = End =
    [01] [00220] WARN  | adrv9025_ClocksSet>  = Start D.Set device clock hsdig divider =
    [01] [00222] WARN  | adi_adrv9025_Initialize> = Start E.Load PFIRs per channel
    [01] [00262] WARN  | adi_adrv9025_Initialize> = End E.Load PFIRs per channel res[0]
    [01] [00263] WARN  | adrv9025_StreamImageLoad> = Start H.Load stream binary =
    [01] [00476] TRACE | adrv9025_StreamImageLoad> = End  H.Load stream binary res [0] =
    [01] [00476] WARN  | adi_adrv9025_PreMcsInit_v2> Start I.Load ARM binary - DPDCORE & ARM
    [01] [00477] TRACE | adrv9025_CpuImageLoad> = Start cpu 0 =
    [01] [02621] TRACE | adrv9025_CpuImageLoad> = Start cpu 1 =
    [01] [03541] TRACE | adrv9025_CpuImageLoad> = End res [0] =
    [01] [03542] WARN  | adi_adrv9025_PreMcsInit_v2> End I.Load ARM binary - DPDCORE res[0]
    [01] [03542] WARN  | adrv9025_LoadRxGainTable> = Start F.Load gain tables =
    [01] [03730] TRACE | adrv9025_LoadRxGainTable> = End F.Load gain tables res [0] =
    [01] [03730] WARN  | adrv9025_LoadTxAttenTable> = Start G.Load Tx attenuation tables =
    [01] [04072] TRACE | adrv9025_LoadTxAttenTable> = End G.Load Tx attenuation tables res [0] =
    [01] [04073] WARN  | adi_adrv9025_PreMcsInit_v2> = Start K.Write init struct =
    [01] [04073] TRACE | adrv9025_AdcProfilesInit> = Start =
    [01] [04074] TRACE | adrv9025_AdcProfilesInit> = End res [0] =
    [01] [04075] WARN  | adi_adrv9025_PreMcsInit_v2> = End K.Write init struct res[0] =
    [01] [04075] WARN  | adi_adrv9025_CpuAdcProfilesWrite> = Start =
    [01] [04085] WARN  | adi_adrv9025_CpuAdcProfilesWrite> = End res [0] =
    [01] [04085] TRACE | adi_adrv9025_CpuProfileWrite> = Start =
    [01] [04117] TRACE | adi_adrv9025_CpuProfileWrite> = End res [0] =
    [01] [04118] WARN  | adi_adrv9025_PreMcsInit_v2> = Start K.Arm boot =
    [01] [04118] WARN  | adi_adrv9025_PreMcsInit_v2> = End K.Arm boot res[0] =
    [01] [04119] WARN  | adi_adrv9025_PreMcsInit_v2>  = End Pre Mcs Init =
    [01] [04119] WARN  | adi_adrv9025_CpuStartStatusCheck> = Start L.Wait for Arm boot complete. & M.verify Arm checksum =
    [01] [04571] WARN  | adi_adrv9025_CpuStartStatusCheck> = End L.Wait for Arm boot complete. & M.verify Arm checksum =
    [01] [04572] WARN  | adi_adrv9025_PreMcsInit_NonBroadCast> = Start M.verify Arm checksum =
    [01] [04572] WARN  | adi_adrv9025_PreMcsInit_NonBroadCast> = End M.verify Arm checksum =
    [01] [04573] WARN  | adi_adrv9025_PreMcsInit_NonBroadCast> = Start RX TX channels Setup =
    [01] [04591] WARN  | adi_adrv9025_PreMcsInit_NonBroadCast> = Start =
    [01] [04591] FATAL | adi_board_adrv9025_Program_Phase1> = End =
    [00] [04592] INFO  | setLogLevel> Module [PLATFORM] log level [8]
    [01] [04592] TRACE | initHWPreMCS> End PreMCS_Init  MAD 1 res=0, duration = 4581[ms]
    [01] [04593] TRACE | initHWPreMCS> Start PreMCS_Init MAD 2
    [00] [04593] INFO  | setLogLevel> Module [PLATFORM] log level [2]
    [01] [04593] FATAL | adi_board_adrv9025_Program_Phase1> = Start =
    [01] [04594] WARN  | adi_adrv9025_HwReset>  = Start A. HW reset =
    [01] [04595] WARN  | adi_adrv9025_HwReset>  = End A. HW reset =
    [01] [04595] WARN  | adi_adrv9025_SpiCfgSet>  = End A.2. Spi config =
    [01] [04596] WARN  | adi_adrv9025_SpiCfgSet>  = Start A.2. Spi verify =
    [01] [04596] WARN  | adi_adrv9025_SpiCfgSet>  = End A.2. Spi verify =
    [01] [04597] WARN  | adi_adrv9025_PreMcsInit_v2>  = Start Pre Mcs Init =
    [01] [04597] WARN  | adrv9025_MasterBiasSet>  = Start B.set master bias =
    [01] [04598] WARN  | adrv9025_MasterBiasSet>  = End B.set master bias res[0] =
    [01] [04799] WARN  | adrv9025_PadConfigsSet> = Start C.Enable pin pads =
    [01] [04800] WARN  | adrv9025_PadConfigsSet> = End C.Enable pin pads res[0] =
    [01] [04800] WARN  | adi_adrv9025_ProfilesVerify> = Start =
    [01] [04801] TRACE | adrv9025_ProfilesVerify> = Start =
    [01] [04801] TRACE | adrv9025_ProfilesVerify> = End res [0] =
    [01] [04802] WARN  | adi_adrv9025_ProfilesVerify> = End =
    [01] [04802] WARN  | adrv9025_ClocksSet>  = Start D.Set device clock hsdig divider =
    [01] [04804] WARN  | adi_adrv9025_Initialize> = Start E.Load PFIRs per channel
    [01] [04845] WARN  | adi_adrv9025_Initialize> = End E.Load PFIRs per channel res[0]
    [01] [04845] WARN  | adrv9025_StreamImageLoad> = Start H.Load stream binary =
    [01] [05059] TRACE | adrv9025_StreamImageLoad> = End  H.Load stream binary res [0] =
    [01] [05060] WARN  | adi_adrv9025_PreMcsInit_v2> Start I.Load ARM binary - DPDCORE & ARM
    [01] [05060] TRACE | adrv9025_CpuImageLoad> = Start cpu 0 =
    [01] [07209] TRACE | adrv9025_CpuImageLoad> = Start cpu 1 =
    [01] [08131] TRACE | adrv9025_CpuImageLoad> = End res [0] =
    [01] [08131] WARN  | adi_adrv9025_PreMcsInit_v2> End I.Load ARM binary - DPDCORE res[0]
    [01] [08132] WARN  | adrv9025_LoadRxGainTable> = Start F.Load gain tables =
    [01] [08320] TRACE | adrv9025_LoadRxGainTable> = End F.Load gain tables res [0] =
    [01] [08320] WARN  | adrv9025_LoadTxAttenTable> = Start G.Load Tx attenuation tables =
    [01] [08662] TRACE | adrv9025_LoadTxAttenTable> = End G.Load Tx attenuation tables res [0] =
    [01] [08663] WARN  | adi_adrv9025_PreMcsInit_v2> = Start K.Write init struct =
    [01] [08663] TRACE | adrv9025_AdcProfilesInit> = Start =
    [01] [08664] TRACE | adrv9025_AdcProfilesInit> = End res [0] =
    [01] [08665] WARN  | adi_adrv9025_PreMcsInit_v2> = End K.Write init struct res[0] =
    [01] [08665] WARN  | adi_adrv9025_CpuAdcProfilesWrite> = Start =
    [01] [08675] WARN  | adi_adrv9025_CpuAdcProfilesWrite> = End res [0] =
    [01] [08675] TRACE | adi_adrv9025_CpuProfileWrite> = Start =
    [01] [08707] TRACE | adi_adrv9025_CpuProfileWrite> = End res [0] =
    [01] [08708] WARN  | adi_adrv9025_PreMcsInit_v2> = Start K.Arm boot =
    [01] [08709] WARN  | adi_adrv9025_PreMcsInit_v2> = End K.Arm boot res[0] =
    [01] [08709] WARN  | adi_adrv9025_PreMcsInit_v2>  = End Pre Mcs Init =
    [01] [08710] WARN  | adi_adrv9025_CpuStartStatusCheck> = Start L.Wait for Arm boot complete. & M.verify Arm checksum =
    [01] [09161] WARN  | adi_adrv9025_CpuStartStatusCheck> = End L.Wait for Arm boot complete. & M.verify Arm checksum =
    [01] [09162] WARN  | adi_adrv9025_PreMcsInit_NonBroadCast> = Start M.verify Arm checksum =
    [01] [09162] WARN  | adi_adrv9025_PreMcsInit_NonBroadCast> = End M.verify Arm checksum =
    [01] [09163] WARN  | adi_adrv9025_PreMcsInit_NonBroadCast> = Start RX TX channels Setup =
    [01] [09181] WARN  | adi_adrv9025_PreMcsInit_NonBroadCast> = Start =
    [01] [09181] FATAL | adi_board_adrv9025_Program_Phase1> = End =
    [00] [09182] INFO  | setLogLevel> Module [PLATFORM] log level [8]
    [01] [09182] TRACE | initHWPreMCS> End PreMCS_Init  MAD 2 res=0, duration = 4589[ms]
    [01] [09183] TRACE | initHWPhaseSynch> Start MCS_Init MAD1 MAD2
    [00] [09183] INFO  | setLogLevel> Module [PLATFORM] log level [2]
    [01] [09184] WARN  | adrv9025_Init_sync> = Start: 1.Reset FPGA RX&TX, 2.Serdes polarity =
    [01] [09284] WARN  | adrv9025_Init_sync> = End 1.Reset FPGA RX&TX, 2.Serdes polarity =
    [01] [09284] FATAL | adi_board_adrv9025_Program_Syncr> = Start =
    [01] [09284] WARN  | adi_board_adrv9025_Program_Syncr> = Start MCS sequence =
    [01] [09291] TRACE | adi_board_adrv9025_Program_Syncr>  stat1=17, stat2 = 17
    [01] [09291] WARN  | adi_board_adrv9025_Program_Syncr> = End MCS sequence =
    [01] [09291] FATAL | adi_board_adrv9025_Program_Syncr> = End =
    [00] [09292] INFO  | setLogLevel> Module [PLATFORM] log level [8]
    [01] [09292] TRACE | initHWPhaseSynch> End MCS_Init MAD1 MAD2 res=0, duration = 109[ms]
    [01] [09293] TRACE | initHWPostMCS> Start PostMCS_Init MAD 1
    [00] [09293] INFO  | setLogLevel> Module [PLATFORM] log level [2]
    [01] [09294] TRACE | adrv9025_Init_PostMCS>  PLL status= 0x1 , res = 0
    [01] [09294] FATAL | adi_board_adrv9025_Program_PostMCS> = Start =
    [01] [09295] WARN  | adi_board_adrv9025_Program_PostMCS> = Start POST MCS sequence =
    [01] [09295] INFO  | adi_adrv9025_PostMcsInit> = Start adi_adrv9025_RxTxEnableSet: Enable the Rx Channels =
    [01] [09298] INFO  | adi_adrv9025_PostMcsInit> = End adi_adrv9025_RxTxEnableSet =
    [01] [09298] INFO  | adi_adrv9025_PostMcsInit> = Start adi_adrv9025_RxTxEnableSet Disable the Rx Channels=
    [01] [09299] INFO  | adi_adrv9025_PostMcsInit> = End adi_adrv9025_RxTxEnableSet =
    [01] [09300] INFO  | adi_adrv9025_PostMcsInit> = Start adrv9025_RadioctrlInit =
    [01] [09300] DEBUG | adrv9025_RadioctrlInit> = Start adi_adrv9025_RadioCtrlCfgSet =
    [01] [09425] DEBUG | adrv9025_RadioctrlInit> = Start adi_adrv9025_StreamGpioConfigSet =
    [01] [09427] DEBUG | adrv9025_RadioctrlInit> = End adi_adrv9025_StreamGpioConfigSet =
    [01] [09428] INFO  | adi_adrv9025_PostMcsInit> = End adrv9025_RadioctrlInit =
    [01] [09428] DEBUG | adrv9025_CalsInit> = Start adi_adrv9025_InitCalsRun =
    [01] [09429] DEBUG | adrv9025_CalsInit> = Start adi_adrv9025_InitCalsWait =
    [01] [20875] DEBUG | adrv9025_CalsInit> = End adi_adrv9025_InitCalsWait =
    [01] [20875] WARN  | adi_board_adrv9025_Program_PostMCS> = End POST MCS sequence =
    [01] [20876] WARN  | adi_board_adrv9025_Program_PostMCS> = Start Serializer reset =
    [01] [20877] WARN  | adi_board_adrv9025_Program_PostMCS> = End Serializer reset =
    [01] [20877] WARN  | adi_board_adrv9025_JesdBringup> = Start =
    [01] [21237] WARN  | adi_board_adrv9025_JesdBringup> = End =
    [01] [21237] INFO  | adi_adrv9025_GpIntInit> = Start =
    [01] [21239] INFO  | adi_adrv9025_GpIntInit> = End =
    [01] [21240] FATAL | adi_board_adrv9025_Program_PostMCS> = End =
    [01] [21240] WARN  | adrv9025_Init_PostMCS> = Start Full duplex link config =
    [01] [21241] DEBUG | JESD_FullDuplexLinkConfig> Set Tx Atten for all channels
    [01] [21242] DEBUG | JESD_FullDuplexLinkConfig> Set Rx Gain for all channels
    [01] [21243] DEBUG | JESD_FullDuplexLinkConfig> Set ObsRx Gain for all channels
    [01] [21244] DEBUG | JESD_FullDuplexLinkConfig> Readback PLL
    [01] [21245] DEBUG | JESD_FullDuplexLinkConfig> LO1 set to :1680000000l0l, res=0
    [01] [21247] DEBUG | JESD_FullDuplexLinkConfig> LO2 set to :1680000000l0l, res=0
    [01] [21248] DEBUG | JESD_FullDuplexLinkConfig> Turning on all Transmitters and Rx1-Rx4 Receivers
    [01] [21249] WARN  | adrv9025_Init_PostMCS> = End Full duplex link config =
    [01] [21250] TRACE | adrv9025_Init_PostMCS>  PLL status= 0xf , res = 0
    [00] [21250] INFO  | setLogLevel> Module [PLATFORM] log level [8]
    [01] [21251] TRACE | initHWPostMCS> End PostMCS_Init  MAD 1  res=0, duration = 11958[ms]
    [01] [21252] INFO  | JESD_ValidateStatus> Channels that are powered up in the transceiver Rx= 0xf, Tx=0xf
    [01] [21253] INFO  | JESD_ValidateStatus> Framers are enabled/disabled = 0x1 , res=0
    [01] [21254] INFO  | JESD_ValidateStatus> Framer status = 0xa
    [01] [21254] INFO  | JESD_ValidateStatus> Deframer Link enable values. reading which deframers are enabled/disabled = 0X1
    [01] [21255] INFO  | JESD_ValidateStatus> Deframer status = 0x87
    [01] [21256] TRACE | initHWPostMCS> Start PostMCS_Init MAD 2
    [00] [21256] INFO  | setLogLevel> Module [PLATFORM] log level [2]
    [01] [21257] TRACE | adrv9025_Init_PostMCS>  PLL status= 0x1 , res = 0
    [01] [21257] FATAL | adi_board_adrv9025_Program_PostMCS> = Start =
    [01] [21258] WARN  | adi_board_adrv9025_Program_PostMCS> = Start POST MCS sequence =
    [01] [21258] INFO  | adi_adrv9025_PostMcsInit> = Start adi_adrv9025_RxTxEnableSet: Enable the Rx Channels =
    [01] [21261] INFO  | adi_adrv9025_PostMcsInit> = End adi_adrv9025_RxTxEnableSet =
    [01] [21261] INFO  | adi_adrv9025_PostMcsInit> = Start adi_adrv9025_RxTxEnableSet Disable the Rx Channels=
    [01] [21262] INFO  | adi_adrv9025_PostMcsInit> = End adi_adrv9025_RxTxEnableSet =
    [01] [21263] INFO  | adi_adrv9025_PostMcsInit> = Start adrv9025_RadioctrlInit =
    [01] [21263] DEBUG | adrv9025_RadioctrlInit> = Start adi_adrv9025_RadioCtrlCfgSet =
    [01] [21387] DEBUG | adrv9025_RadioctrlInit> = Start adi_adrv9025_StreamGpioConfigSet =
    [01] [21389] DEBUG | adrv9025_RadioctrlInit> = End adi_adrv9025_StreamGpioConfigSet =
    [01] [21390] INFO  | adi_adrv9025_PostMcsInit> = End adrv9025_RadioctrlInit =
    [01] [21390] DEBUG | adrv9025_CalsInit> = Start adi_adrv9025_InitCalsRun =
    [01] [21391] DEBUG | adrv9025_CalsInit> = Start adi_adrv9025_InitCalsWait =
    [01] [32758] DEBUG | adrv9025_CalsInit> = End adi_adrv9025_InitCalsWait =
    [01] [32758] WARN  | adi_board_adrv9025_Program_PostMCS> = End POST MCS sequence =
    [01] [32759] WARN  | adi_board_adrv9025_Program_PostMCS> = Start Serializer reset =
    [01] [32760] WARN  | adi_board_adrv9025_Program_PostMCS> = End Serializer reset =
    [01] [32760] WARN  | adi_board_adrv9025_JesdBringup> = Start =
    [01] [33121] WARN  | adi_board_adrv9025_JesdBringup> = End =
    [01] [33121] INFO  | adi_adrv9025_GpIntInit> = Start =
    [01] [33123] INFO  | adi_adrv9025_GpIntInit> = End =
    [01] [33124] FATAL | adi_board_adrv9025_Program_PostMCS> = End =
    [01] [33124] WARN  | adrv9025_Init_PostMCS> = Start Full duplex link config =
    [01] [33125] DEBUG | JESD_FullDuplexLinkConfig> Set Tx Atten for all channels
    [01] [33126] DEBUG | JESD_FullDuplexLinkConfig> Set Rx Gain for all channels
    [01] [33127] DEBUG | JESD_FullDuplexLinkConfig> Set ObsRx Gain for all channels
    [01] [33128] DEBUG | JESD_FullDuplexLinkConfig> Readback PLL
    [01] [33129] DEBUG | JESD_FullDuplexLinkConfig> LO1 set to :1680000000l0l, res=0
    [01] [33131] DEBUG | JESD_FullDuplexLinkConfig> LO2 set to :1680000000l0l, res=0
    [01] [33132] DEBUG | JESD_FullDuplexLinkConfig> Turning on all Transmitters and Rx1-Rx4 Receivers
    [01] [33133] WARN  | adrv9025_Init_PostMCS> = End Full duplex link config =
    [01] [33134] TRACE | adrv9025_Init_PostMCS>  PLL status= 0xf , res = 0
    [00] [33134] INFO  | setLogLevel> Module [PLATFORM] log level [8]
    [01] [33135] TRACE | initHWPostMCS> End PostMCS_Init  MAD 2  res=0, duration = 11879[ms]
    [01] [33136] INFO  | JESD_ValidateStatus> Channels that are powered up in the transceiver Rx= 0xf, Tx=0xf
    [01] [33137] INFO  | JESD_ValidateStatus> Framers are enabled/disabled = 0x1 , res=0
    [01] [33138] INFO  | JESD_ValidateStatus> Framer status = 0xa
    [01] [33139] INFO  | JESD_ValidateStatus> Deframer Link enable values. reading which deframers are enabled/disabled = 0X1
    [01] [33139] INFO  | JESD_ValidateStatus> Deframer status = 0x87

    Hi,

    I attached the relevant portion of our SW log. The two ADRV9026 parts are referred to as MAD1 and MAD2.

    Thanks!

  • 0
    •  Analog Employees 
    on Jul 22, 2021 12:55 PM in reply to haimf

    If same LO is used for all 4 channels , You can use single LO.

    How are you measuring LO Phase Sync ? 

    Make sure that Sysref and Device clocks are aligned across the 2 Transceivers and FPGA from boot to Boot.

    Can you share your clock scheme.? What is the device clock and sysref frequency used? 

  • We are already using a single LO within each transceiver IC for 4 channels each. Our problem is syncing the LOs across the 2 ICs, which is not working.

    We measured the LO Phase Sync indirectly by splitting the output of a signal generator whose frequency is offset from the carrier frequency by several MHz to 2 RX channels (one on each transceiver IC) and measuring the phase between the baseband samples. We don't care about the phase value itself so long as it is fixed and consistent at every power up. Right now we are getting random phase differences at every power up.

    The SYSREF and DEVCLK signals are aligned and consistent from boot to boot.

    The DEVCLK frequency is 245.76 MHz. We are using LTC6953 to distribute DEVCLK and SYSREF.

  • Can you please send us a working example of an init sequence which synchronizes 2 or more ADRV9026 ICs, including PLL phase sync?

  • 0
    •  Analog Employees 
    on Jul 25, 2021 12:18 PM in reply to haimf

    Can you measure FIFO depth in FPGA deframer for both instances. if there is FIFO depth variation from boot to boot phase can vary.

    Please make sure you are enabling the " Enable RFPLL phase sync init and track continuously" in the init data.c.

    Other than enabling Phase sync init and running tracking cal there are no other requirement for RF PLL phase sync , Its a slow continuous loop which maintains LO phase same as Device clock phase. 

    If you re-program and measure phase within same power up are you able to see same relative phase between Rx1 of two different ADRV902x device. ? 

  • Hello Vinod,

    The FIFO depth is fixed in firmware, so it cannot change from boot to boot.

    Regarding your question: each time we perform the init routine, without powering down the board, we see different phases between the two ICs (measuring relative phase of one RX channel from each IC).

    I have several questions/comments to which I would appreciate your response:

    1) Please review the logfile I sent earlier and confirm that we are performing the steps correctly, or even better, please send us a working example of a multi-chip initialization code.   

    2) What are the requirements for the SYSREF and DEVCLK signals in order to ensure proper operation of the phase sync mechanism? How many SYSREF pulses, SYSREF pulse width, time interval between the SYSREF pulses, rise/fall times, relative DEVCLK-SYSREF timing, etc.

    3) Does changing the LO frequency require re-syncing the phase?

    Thanks!

  • 0
    •  Analog Employees 
    on Jul 26, 2021 8:41 AM in reply to haimf

    FIFO depth depends on the release point of the elastic buffer and it should not be fixed. If issue is seen from Boot to boot try reading the buffer depth from FPGA.

    Within same boot up, if you run only init calibration and not run JESD bring up are you seeing a phase difference.?

    With same boot up, If you stop the input signal and send signal again and measure are you seeing phase variation ? 

    You can try disabling tracking cals and measure phase if you still see variation. 

    1)From log you are getting MCS status =0x17 which is correct. Please share initdata.c file as well.

    2)Sysref and dev clock should meet the timing requirement specified in datasheet and user guide. We need 4 sysref pulse for MCS. In software we send multiple sysref (255) until an MCS status of 0x17 is achieved. 

    what is the sysref frequency used ? 

    3)If ADI_ADRV9025_RFPLLMCS_INIT_AND_CONTTRACK is enabled in adi_adrv9025_RfPllMcs it will automatically sync the phase. The phase Sync loop is a slow loop and it will take some time to align the phase.