We have developed a board which uses two ADRV9026 chips to implement 8 TX and 8 RX channels. After the initialization process, we expected to have a fixed, consistent phase relationship between the two ADRV9026 chips, since according to the UG-1727 System Development User Guide, the LO PLLs are phase-aligned at the MCS stage of the initialization. However, we have different phase relationships every time we power up the board. The JESD204B interface works fine and the statuses seem to be OK. What could be the reason for this problem?
[edited by: haimf at 12:31 PM (GMT -4) on 20 Jul 2021]