ADRv9026: JESD Bring Up Sequence

Hi All,

I was doing JESD204B bring up in ADRV9025. I read the below ink and other related stuff. 


https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9026/f/q-a/120972/adrv9026-framer-link-set-up-procedure

I have few doubts in this. 

1) What is use of overriding FPGA side DFE LPM in PHY before sending SYSREF

2)  In the above link, we are using single shot SYSREF. Though, we should have minimum 3 clock pulses to sync various block of adrv9010 so how can single shot can sync various block? 

3) I have configured continuous SYSREF pattern instead of single shot so do I need to follow step (8)  of the above link ? 

Regards,

Manish

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