Questions about "Figure 64. ORx Enable and Tx Select Signals: 4 Tx, 4 Rx, 2 ORx Configuration"

The figure below is "Figure 64. ORx Enable and Tx Select Signals: 4 Tx, 4 Rx, 2 ORx Configuration" in UG-1727.

Here, is the control signal that ORX2/3_TX_SEL is output from the FPGA?

As an additional question, is the direction of GPIO_X/Y shown in the figure input? Is it output?

Also, is there a way to know if the calibrations Tx1/Tx2 times have expired?