ADRV9026 SERDES Polarity

I just noticed in the schematics for the SERDIN/OUT lanes that they are mixed polarity going through the FMC interface back to our custom motherboard. I am a little confused on how to handle this to fix the polarity. I noticed in the initdata file that there is a adi_adrv9025_SerCfg_t and adi_adrv9025_DesCfg_t array that has an option to invert lane polarity. I mean specifically this section

typedef struct adi_adrv9025_SerCfg
{
    uint8_t serAmplitude;                       /*!< Serializer amplitude setting. Default = 1. (Range is 0..3) 0 = 1.0 * VTT, 1 = 0.85*VTT, 2 = 0.75*VTT, 3 = 0.5*VTT */
    uint8_t serPreEmphasis;                     /*!< Serializer pre-emphasis setting. Default = 0 (Range is 0..2) , 0=0dB, 1=3dB, 2=6dB*/
    uint8_t serPostEmphasis;                    /*!< Serializer Post-emphasis setting. (Valid 0,1,2,3,4) 0=0dB, 1=3dB, 2=6dB, 3=9dB, 4=12dB */
    uint8_t serInvertLanePolarity;              /*!< Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
} adi_adrv9025_SerCfg_t;

/**
*  \brief Data structure to hold ADRV9025 JESD204b Deserializer configuration information
*/
typedef struct adi_adrv9025_DesCfg
{
    uint8_t desInvertLanePolarity;      /*!< Deserializer Lane PN inversion select.  1 = Invert PN, 0 = Do nothing */
    uint8_t highBoost;                  /*!< High Boost Lane enable select. 1 = High Boost enabled, 0 = High Boost disabled */
    uint32_t configOption1;             /*!< SERDES init & tracking calibration algorithm parameter */
    uint32_t configOption2;             /*!< SERDES init & tracking calibration algorithm parameter */
    uint32_t configOption3;             /*!< SERDES init & tracking calibration algorithm parameter */
    uint32_t configOption4;             /*!< SERDES init & tracking calibration algorithm parameter */
    uint32_t configOption5;             /*!< SERDES init & tracking calibration algorithm parameter */
    uint32_t configOption6;             /*!< SERDES init & tracking calibration algorithm parameter */
    uint32_t configOption7;             /*!< SERDES init & tracking calibration algorithm parameter */
    uint32_t configOption8;             /*!< SERDES init & tracking calibration algorithm parameter */
    uint32_t configOption9;             /*!< SERDES init & tracking calibration algorithm parameter */
    uint32_t configOption10;            /*!< SERDES init & tracking calibration algorithm parameter */
} adi_adrv9025_DesCfg_t;

My question is on the comments next to the serInvertLanePolarity. Why does it talk about different bits enabling different lanes, if there are four SerCfg structures in the init data file? If I need to flip the polarity on each of the Serializer lines headed back to my FPGA, should these serInvertLanePolarity be 0x1 or 0xF or something else?


{  // serCfg (array)
        {  // serCfg[0]
            0,  // serAmplitude
            0,  // serPreEmphasis
            0,  // serPostEmphasis
            1   // serInvertLanePolarity
        },
        {  // serCfg[1]
            0,  // serAmplitude
            0,  // serPreEmphasis
            0,  // serPostEmphasis
            1   // serInvertLanePolarity
        },
        {  // serCfg[2]
            0,  // serAmplitude
            0,  // serPreEmphasis
            0,  // serPostEmphasis
            1   // serInvertLanePolarity
        },
        {  // serCfg[3]
            0,  // serAmplitude
            0,  // serPreEmphasis
            0,  // serPostEmphasis
            1   // serInvertLanePolarity
        }
        }, // serCfg (end of array)