ADRV9026 can support lane rates of up to 25Gbps in JESD204C mode. For 25Gbps, ADI recommends to have the insertion loss over the SERDES lanes to be in the range of 4-9dB over the entire range of operating temperature. This insertion loss includes any PCB related insertion losses including the AC coupling capacitor (ball to ball). Please note that the 4-9dB IL range does not include the package insertion loss. The user should not worry about the package insertion loss as this is already accounted for. For uses cases operating at 25G, ADI recommends the following based on the number of lanes used –If L = 1 (on the deframer side), Lane A is recommended.If L = 2 (on the deframer side), For this case, either lanes A and C or lanes B and D are recommended to minimize crosstalk possibilities. Please note that ADRV9026 do not have any integrated crosstalk noise specification. At IL range of 4-9dB, the expected crosstalk should be very minimal.
ADI recommends the following configuration for the JRx and JTx for ADRV9026 as well as JRx and JTx configuration on FPGA (ASIC) side for optimal 25G performance using SW220.127.116.11 for ADRV9026 B0 silicon –Recommendation for JTx (FPGA (ASIC) side) -> JRx (ADRV9026 side) –
• For JRx_ADRV9026_side –"highBoost": 0,"configOption1": 0,"configOption2": 0,"configOption3": 0,"configOption4": 0,"configOption5": 0,"configOption6": 0,"configOption7": 0,"configOption8": 0,"configOption9": 0,"configOption10": 0,"desInvertLanePolarity": 0
• For JTx_FPGA(ASIC)_Side –The Swing is recommended to be in between 700mV to 850mV.For 700mV – the eye opening should be around 558mVFor 850mV – the eye opening should be around 684mVThe user can use the above JTx_FPGA(ASIC)_Side eye requirements to obtain the emphasis settings needed on their FPGA (ASIC) side to talk to ADRV9026 at 25G. For BER of 1e-11, JRx_ADRV9026 would require +/- 4 good phases on each side of the eye or 0.25UI to get optimum performance at 25G. This is the horizontal eye requirement for ADRV9026 (JRx side). JRx_ADRV9026 does not have any vertical eye requirement.
Recommendation for JTx (ADRV9026 side) -> JRx (FPGA (ASIC) side) –
• For JTx_ADRV9026_Side –"serAmplitude": 0,"serPreEmphasis": 0,"serPostEmphasis": 0,"serInvertLanePolarity": 0
• For JRx_FPGA(ASIC)_Side –No specific recommendationFor this case, it is expected that the user would tune the JTx settings on the ADRV9026 side using a PRBS based signal integrity tests.