I am configuring the ADRV9026 to work with the Xilinx ZCU106 board and am trying to establish the JESD link between the two boards and was wondering where in the initialization sequence I was supposed to bring the different cores out of reset? Where in the ADRV API are their Tx/Rx cores and PHYs brought out of reset? When should I bring my own out of reset?
Please refer to the below posts,
Are we supposed to call adi_board_adrv9025_JesdBringup() ?
Thanks for this information. Following this advice, I've been able to setup the Transceiver path and am working on getting the receiver path stable as well.Now that I have the transmit path, however, I should be able to move samples to the transceiver and see the analog signal, correct? The format that I'm trying to save data in before transmitting one sample is (<int16 I><int16 Q>). Does this seem correct?
To add some more information, we are only using the first deframer for Tx1 and Tx2. Our profile looks like below
Refer to the below post for the format:
You can directly use any of the data files(set the required sampling rate) available in the below link :
Okay, that's helpful thanks. I see that's for different JESD setup than I'm using, how do I map that format to my setup?
The format is MSB first then LSB should go the chip for transmitting.