ADRV9026 - Choosing Devclk, sysref and JESD profile

Hi,

We were using AD9375 platform earlier with highlighted JESD rates and profile. With minimum changes in JESD IQ data interfaces and not so high sample rates, I am trying to rebuild profile with ADRV.

Now, we have ADRV9026 Transceiver which has 4T4R along with 4 ORX. We want to have a profile where complete 4T4R system being used and don't want to route any ORX paths into FPGA which I believe is called non link sharing mode (NLS).

1. I have a doubt in choosing devclk for RF and FPGA, I believe it is 245.76MHz(as I see this value often mentioned in datasheet). Is it correct ? I exactly don't know on what basis we have to  choose devclk frequency or does transceiver come with standard/fixed dev clock rate ? Also, can I have tx/rx_sysref = samplerate/(k*N) of 7.68MHz where N being 1 and rate= 245.76MHz

2..I have chosen highlighted(blue ticked) profile for DAC path(datasheet), where LMFS = 4841 with JESD204B linerate = 9.8Gbps. In GUI demo mode only I could see 3 profiles being listed. I chose lower sample rate profile -> 13_NLS profile. 

3.Similarly for ADC path(blue ticked), LMFS = 2841 with JESD204B linerate = 9.8 Gbps, fs = 245.76. But I want to use 4 lanes for receive addressing 4R channels. So, Corresponding GUI in demo mode with 13_NLS profile I modified JESD204B framer 0 to have 4 lanes and other framers unused. So, can we have this LMFS = 4841 with linerate = 4.9 Gbps, fs = 122.88MHz with 4 lanes being used and utilizing all 4 receive channels?

4. Other settings unchanged and left to default in GUI. Is the following default clock setting in GUI is proper?

So, with the above attached GUI settings, code dumps is taken. Is the above JESD204B TX/RX profile a valid one?



.
[edited by: rakshi at 11:19 AM (GMT -4) on 21 Oct 2020]
  • 0
    •  Analog Employees 
    on Oct 22, 2020 8:27 AM 1 month ago
    I have a doubt in choosing devclk for RF and FPGA, I believe it is 245.76MHz(as I see this value often mentioned in datasheet). Is it correct ? I exactly don't know on what basis we have to  choose devclk frequency or does transceiver come with standard/fixed dev clock rate ? Also, can I have tx/rx_sysref = samplerate/(k*N) of 7.68MHz where N being 1 and rate= 245.76MHz

    Yes. 245.76MHz is the default DEV_CLK frequency. DEV_CLK frequency should be chosen such that it is integer multiple of the VCXO frequency.

    Typically the SYSREF frequency is 120KHz. You can configure sysref as continious for test purpose and  trigger and capture the Sysref pulse to know the sysref frequency.

    Yes. The GUI clock and JESD settings are correct and you can use it.