In ADRV9026, the user has the option of enabling gain compensation in the device. In gain compensation mode, the digital gain block is utilized to compensate for the analog front-end attenuation. The digital gain block is controlled by the gain table, and a compensated gain table is required to operate in this mode. ADI provides an example compensated gain table in the software package. Such a gain table has a unique front-end attenuator setting with a corresponding amount of digital gain programmed at each index of the table. Gain compensation can be used in either AGC or MGC modes. The maximum amount of gain compensation is 50 dB. This allows for compensation of both the internal analog attenuator and an external gain component (such as a DSA or LNA). Large amounts of digital gain increase the bit width of the path. There are a number of ways in which this expanded bit-width data can be sent to the baseband processor, which are detailed below. Figure below is a block diagram of the gain compensation portion of the Rx chain, showing the locations of the various blocks.
The slicer is used to attenuate the data after the digital gain block such that it can fit into the resolution of the JESD data path. It then advises the user how much attenuation is being applied in real time, so that the user can compensate on the baseband processor side. In this mode, the current slicer setting (amount of attenuation) is provided in 3 different ways (described below). The slicer bits are received by the BBP to scale the power of the received signal and determine the power at the input to the device (or at the input to an external gain element if considered part of the digital gain compensation). There are 3 different ways to transmit the slicer bits to the BBP, as listed below –
There are 3 methods that the user can use to obtain the slicer information during gain compensation mode -
In this mode, instead of transmitting the slicer bits over the GPIO, the slicer bits are embedded in the Rx data to be transmitted to the BBP. There are a number of permissible ways in which this can be configured, controlled by the intEmbeddedBits API parameter. The user can place the slicer setting as 1 bit on both I and Q, or 2 bits on both I and Q. These can be placed at the MSBs or LSBs. As an example in 12 bit output mode, for the case where 1 bit is embedded onto both I and Q data, the total of 2 bits will be used for slicer information and the remaining 11 bits would be normal user data. In this case, 4 slicer positions could be supported. Please refer to the ADRV9026 user guide for detailed format of each of these different embedded slicer modes. Please note that there is a minor hit to the Rx SNR due to usage of embedded slicer mode (moving from 12 data bits to 11 data bits).
This mode is similar to embedded slicer mode but instead of continuously transmitting the slicer bits as part of Rx data, the slicer information is only transmitted when a gain change occurs. This allows the receiver to transmit the full data word to the baseband processor unless the slicer word needs to be transmitted. This maximizes the SNR performance of the receiver. A dynamic slicer packet is transmitted whenever a gain change occurs. This packet is composed of three segments for a total of 56-bits:
The format for transmitting this packet is CRC word first, followed by the slicer word and finally the Sync Header. The user can use the SYNC header to check if the received sequence has the dynamic slicer word or not. A snapshot of the dynamic slicer packet transmission is shown below in the sequence it is output from the part –
Since the dynamic slicer packet is transmitted over multiple samples, sometime is taken to transmit the entire word. In the case above, the data rate is 245.76 MSPS. This data rate requires 114 ns to transmit the entire dynamic slicer packet.