ADRV9026 Deframer Link Deterministic Latency

The user can refer to the “ SELECTING THE OPTIMAL LMFC/LEMC OFFSET FOR A DEFRAME “ section in the ADRV9026 user guide to know how to optimize the LMFC/LEMC offset for deframer to get deterministic latency. There are three methods to program the LFMC/LEMC offset for a given deframer :
1. By modifying the profile file being used
2. By using the adi_adrv9025_DfrmCfg data structure
3. By writing directly to the relevant SPI registers
The first two ways need to re-program the chip after change the setting. In order to reduce the LMFC/LEMC sweep time. It is possible to set the LMFC/LEMC offset value by writing to the following SPI registers:
1. Deframer0 LMFC/LEMC offset control register:
A. Register 0x6A8E, Bits[7:0]: jrx_tpl_phase_adjust[7:0]. Bits[7:0] of the LMFC/LEMC phase adjustment 16-bit word for Deframer 0. The valid range of phase adjustment values is 0 to (K × S) − 1 (where K is the number of frames per multiframe/extended multiblock, and S is the number of samples per converter per frame cycle).
B. Register 0x6A8F, Bits[7:0]: jrx_tpl_phase_adjust[15:8]. Bits[15:8] of the LMFC/LEMC phase adjustment 16-bit word for Deframer 0. The valid range of phase adjustment values is 0 to (K × S) − 1 (where K is the number of frames per multiframe/extended multiblock, and S is the number of samples per converter per frame cycle).
2. Deframer1 LMFC/LEMC offset control register:
A. Register 0x6C8E, Bits[7:0]: jrx_tpl_phase_adjust[7:0]. Bits[7:0] of the LMFC/LEMC phase adjustment 16-bit word for Deframer 1. The valid range of phase adjustment values is 0 to (K × S) − 1 (where K is the number of frames per multiframe/extended multiblock, and S is the number of samples per converter per frame cycle).
B. Register 0x6C8F, Bits[7:0]: jrx_tpl_phase_adjust[15:8]. Bits[15:8] of the LMFC/LEMC phase adjustment 16-bit word for Deframer 1. The valid range of phase adjustment values is 0 to (K × S) − 1 (where K is the number of frames per multiframe/extended multiblock, and S is the number of samples per converter per frame cycle).
Note that a SYSREF pulse must be applied and then the link between the baseband JESD framer and JESD deframer of the transceiver must be reestablished after changing the LMFC/LEMC offset through SPI writes for a given deframer for the change to take effect.