ADRV9026 Framer Link Deterministic Latency

The user can refer to the “ Deterministic Latency in JESD204C Mode “ in the ADRV9026 user guide to get the information how to get the deterministic latency in JESD204C mode. If user find some issues related with the framer link deterministic latency, they can follow below instructions to identify the root cause:
1. Make sure the sysref vs device clock setup & hold time can meet the timing requirements specified in the ADRV9026 datasheet;
2. Call API function adi_adrv9025_MultichipSyncStatusGet to get MCS status and make sure each power up the MCS status is 0x17, Refer to API CHM help file to get each bit description;
3. Call API function adi_adrv9025_FramerStatusGet to make sure framer link is built up. The read back value after link bring up should be 0xA for 204B and 0x2 for 204C;
4. The sysref can be one shot or N shot mode . ADI recommend to use one shot mode. The user need to guarantee the “ sysrefNShotEnable “ & “sysrefNShotCount “ parameter in framer section of initialization configuration file match with the hardware implementation;
5. The user need to guarantee the sysref phase keep constant between MCS(Multi Chip Synchronization) stage and JESD set up stage from power up to power up;
6. If the sysref is one shot mode. The user need to make sure the first sysref phase keep constant from power up to power up, The sysref signal physical characteristics need to meet the “ DIGITAL SPECIFICATIONS(LVDS)”section in the ADRV9026 datasheet;
7. Adjust the LMFC/LEMC to of ADRV9026 make the baseband side chip deframer FIFO depth at the middle value. There are three methods to program the LFMC/LEMC offset for a given framer :
     A. By modifying the profile file being used
     B. By using the adi_adrv9025_FrmCfg data structure
     C. By writing directly to the relevant SPI registers
 The first two ways need to re-program the chip after change the setting. In order to reduce the LMFC/LEMC sweep time. It is possible to set the LMFC/LEMC offset value by writing to the             following SPI registers:

 Framer0 LMFC/LEMC offset control register:
     --- Register 0x6E3F, Bits[7:0]: jtx_tpl_phase_adjust[7:0]. Bits[7:0] of the LMFC/LEMC phase adjustment 16-bit word for Framer 0. The valid range of phase adjustment values is 0 to (K × S) −       1 (where K is the number of frames per multiframe/extended multiblock, and S is the number of samples per converter per frame cycle).
     ---Register 0x6E40, Bits[7:0]: jtx_tpl_phase_adjust[15:8]. Bits[15:8] of the LMFC/LEMC phase adjustment 16-bit word for Framer 0. The valid range of phase adjustment values is 0 to (K × S)       − 1 (where K is the number of frames per multiframe/extended multiblock, and S is the number of samples per converter per frame cycle).

 Framer1 LMFC/LEMC offset control register:
     ---Register 0x703F, Bits[7:0]: jtx_tpl_phase_adjust[7:0]. Bits[7:0] of the LMFC/LEMC phase adjustment 16-bit word for Framer 1. The valid range of phase adjustment values is 0 to (K × S) −       1 (where K is the number of frames per multiframe/extended multiblock, and S is the number of samples per converter per frame cycle).
     ---Register 0x7040, Bits[7:0]: jtx_tpl_phase_adjust[15:8]. Bits[15:8] of the LMFC/LEMC phase adjustment 16-bit word for Framer 1. The valid range of phase adjustment values is 0 to (K × S)       − 1 (where K is the number of frames per multiframe/extended multiblock, and S is the number of samples per converter per frame cycle).

 Note that a SYSREF pulse must be applied and then the link between the baseband JESD deframer and JESD framer of the transceiver must be reestablished after changing the LMFC/LEMC offset through SPI writes for a given framer for the change to take effect.