ADRV9026 PCB Design Rule

The user can refer to the “ PCB LAYOUT CONSIDERATIONS “ section in ADRV9026 user guide to get the detailed PCB design guidance. Customer can also refer to the ADI EVB board in ADRV9026 design file package to know how ADI place the component and design the routing . Some general PCB layout design rule list as below:
1. Different type signal routing need to be prioritized: RF inputs and outputs, clocks, and high speed digital signals are the most critical for optimizing performance and must be routed with the highest priority. Power supply routing and quality has a direct impact on overall system performance, Need to be considered as second priority. The third priority is to route remaining low frequency digital inputs and outputs, auxiliary ADCs and DACs, and SPI signals.
2. It is important to route all digital signals away from sensitive analog signals on PCB signal layers with a solid ground layer which can shield other sensitive signals from the potentially noisy digital signals.
3. Device clock amplitude is a little higher and has many high order harmonic products, This signal will be aggressor to other sensitive analog signal like Tx/Rx/ORx. Need to provide enough isolation between device clocking routing and Tx/Rx/ORx signal. The user also need to pay attention to provide the enough isolation between device clock and Tx balun DC feed 1.8V power supply which present on the Tx output port directly. Connect external clock inputs to DEVCLK+ and DEVCLK− through ac coupling capacitors. AC coupling capacitors can be put at the clock source side. Then route the DEVCLK+/- at internal layer . Shield this trace by ground planes above and below with vias staggered along the edges of the differential pair routing. Place a 100 Ω termination across the input near Pin C8 and Pin C9.
4. To the Tx balun DC feed 1.8V power supply. The RF chokes must be decoupled by capacitors from the power feed to ground. Place the ground connections to these bypass capacitors as close as possible to the Tx output pins. Take care to match both chokes and their layout to avoid peaking due to current transients.
5. To JESD204C high speed serial interface. To avoid the lane clock high order harmonic product interfere the Tx/Rx/ORx. ADI recommend to place the ac coupling capacitors (100 nF) away from the chip.
6. To the JESD204C routing trace length. The trace insertion loss is better to be controlled in ADI recommended range.
7. To each power supply pin, Place the smallest bypass capacitor to the pin as close as possible.