The user can refer to the ADRV9026 user guide to know the chip basic working theory. Customer can also refer to the ADI EVB board schematic file in ADRV9026 design file package to get the EVB schematic design detail. Some general schematic design rule list as below:1. Refer to the “ UNUSED PIN INSTRUCTIONS “ table in ADRV9026 user guide to get the unused pin design method. Unused GPIO_ANA_n/GPIO_n pins can be connected to VSSA with a 10 kΩ resistor or configure as outputs, drive low, and leave disconnected.2. Before start to configure the chip, Need to hardware reset the chip. Hardwire reset pin RESETB need to be connected to BB side and control by baseband chip.3. TEST_EN (P10) pin have JTAG function. Test Input for JTAG Boundary Scan. Pull high to enable boundary scan. For normal working mode need to be tied to VSSA.4. Rbias(C15) generates an internal current based on an external 1% resistor. Connect a 4.99 kΩ resistor between Pin C15 and analog ground (VSSA).5. SPI output driver strength is limited, Don’t put big bypass capacitance on it. Customer need to guarantee the signal integrity on their system board. Refer to “ SPI Bus Setup Parameters ”table in ADRV9026 user guide to get the CMOS pad driver strength.6. LVDS type SYSREF prefer to use N*pulse mode. Request to use DC couple mode not AC couple mode. Clock chip should have the capability to generate the N*pulse SYSREF and can be disabled/enabled. Need to check the SYSREF common mode voltage also to make sure two sides match with each other; There are no internal 100ohm termination inside chip. Need to add external 100ohm termination.7. It is better to have a test point for SYNC signal. Make sure the SYNC is DC couple and have correct common mode voltage match with each side.8. There are DC voltage presented on the RX&ORX input pin, Make sure the AC capacitor on the P/N port will not be replaced with inductor when do match network design.9. ADI recommend to use central DC feed balun, Not feed DC through two inductor, If customer use inductor to do DC feed. Need to select proper inductor value to make sure this inductor value is smaller as possible but can prevent the main signal leakage into power supply domain and make the output signal power lower than expected. The main reason to use smaller inductor is to make P end and N end match with each other easier .Otherwise when change the TXATT in big step. Customer can see a glitch due to this inductor mismatch. In the system. It is better to change the TXATT in small step , Like if customer need to change from 0dB to 20dB, It is better to implement it in small step10. Make sure the Tx PA driver & PA can be powered down when do TX initialization calibration.11. The selected JESD lanes are better to align with ADI recommended lanes.12. Make sure the Rx/ORx input port power is less than -78dBm/1MHz when do Rx/ORx OTC initialization calibration. Customer may need to power down the Rx front end low noise amplifier or terminate the input port with 50ohm load by RF switch.13. Make sure the power supply voltage variation meet the min/max request in the ADRV9026 datasheet.14. Make sure the chip power supply power up/power down sequence can meet the request defined in the ADRV9026 datasheet.